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https://github.com/c64scene-ar/llvm-6502.git
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1ebbc68719
This patch adds support for the vector merge even word and vector merge odd word instructions introduced in POWER8. Phabricator review: http://reviews.llvm.org/D10704 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240650 91177308-0d34-0410-b5e6-96231b3b80d8
102 lines
3.9 KiB
LLVM
102 lines
3.9 KiB
LLVM
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-LE
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-BE
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; Check for a vector merge instruction using two inputs
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; The shufflevector specifies the even elements, using big endian element
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; ordering. If run on a big endian machine, this should produce the vmrgew
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; instruction. If run on a little endian machine, this should produce the
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; vmrgow instruction. Note also that on little endian the input registers
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; are swapped also.
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define void @check_merge_even_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK-LE-LABEL: @check_merge_even_xy
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; CHECK-BE-LABEL: @check_merge_even_xy
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3,
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i32 16, i32 17, i32 18, i32 19,
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i32 8, i32 9, i32 10, i32 11,
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i32 24, i32 25, i32 26, i32 27>
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; CHECK-LE: vmrgow 2, 3, 2
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; CHECK-BE: vmrgew 2, 2, 3
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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; CHECK-LE: blr
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; CHECK-BE: blr
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}
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; Check for a vector merge instruction using a single input.
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; The shufflevector specifies the even elements, using big endian element
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; ordering. If run on a big endian machine, this should produce the vmrgew
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; instruction. If run on a little endian machine, this should produce the
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; vmrgow instruction.
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define void @check_merge_even_xx(<16 x i8>* %A) {
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entry:
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; CHECK-LE-LABEL: @check_merge_even_xx
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; CHECK-BE-LABEL: @check_merge_even_xx
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp,
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<16 x i32> <i32 0, i32 1, i32 2, i32 3,
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i32 0, i32 1, i32 2, i32 3,
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i32 8, i32 9, i32 10, i32 11,
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i32 8, i32 9, i32 10, i32 11>
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; CHECK-LE: vmrgow 2, 2, 2
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; CHECK-BE: vmrgew 2, 2, 2
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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; CHECK-LE: blr
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; CHECK-BE: blr
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}
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; Check for a vector merge instruction using two inputs.
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; The shufflevector specifies the odd elements, using big endian element
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; ordering. If run on a big endian machine, this should produce the vmrgow
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; instruction. If run on a little endian machine, this should produce the
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; vmrgew instruction. Note also that on little endian the input registers
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; are swapped also.
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define void @check_merge_odd_xy(<16 x i8>* %A, <16 x i8>* %B) {
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entry:
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; CHECK-LE-LABEL: @check_merge_odd_xy
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; CHECK-BE-LABEL: @check_merge_odd_xy
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2,
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<16 x i32> <i32 4, i32 5, i32 6, i32 7,
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i32 20, i32 21, i32 22, i32 23,
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i32 12, i32 13, i32 14, i32 15,
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i32 28, i32 29, i32 30, i32 31>
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; CHECK-LE: vmrgew 2, 3, 2
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; CHECK-BE: vmrgow 2, 2, 3
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store <16 x i8> %tmp3, <16 x i8>* %A
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ret void
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; CHECK-LE: blr
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; CHECK-BE: blr
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}
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; Check for a vector merge instruction using a single input.
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; The shufflevector specifies the odd elements, using big endian element
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; ordering. If run on a big endian machine, this should produce the vmrgow
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; instruction. If run on a little endian machine, this should produce the
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; vmrgew instruction.
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define void @check_merge_odd_xx(<16 x i8>* %A) {
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entry:
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; CHECK-LE-LABEL: @check_merge_odd_xx
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; CHECK-BE-LABEL: @check_merge_odd_xx
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%tmp = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp,
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<16 x i32> <i32 4, i32 5, i32 6, i32 7,
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i32 4, i32 5, i32 6, i32 7,
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i32 12, i32 13, i32 14, i32 15,
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i32 12, i32 13, i32 14, i32 15>
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; CHECK-LE: vmrgew 2, 2, 2
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; CHECK-BE: vmrgow 2, 2, 2
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store <16 x i8> %tmp2, <16 x i8>* %A
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ret void
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; CHECK-LE: blr
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; CHECK-BE: blr
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}
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