Nadav Rotem 9f40cb32ac Not all targets have efficient ISel code generation for select instructions. ... For example, the ARM target does not have efficient ISel handling for vector selects with scalar conditions. This patch adds a TLI hook which allows the different targets to report which selects are supported well and which selects should be converted to CF duting codegen prepare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163093 91177308-0d34-0410-b5e6-96231b3b80d8		2012-09-02 12:10:19 +00:00
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ARM	Not all targets have efficient ISel code generation for select instructions.	2012-09-02 12:10:19 +00:00
CellSPU	Add test triples to fix win32 failures. Revert workaround from r161292.	2012-08-08 20:31:37 +00:00
CPP	test commit	2012-07-18 17:53:05 +00:00
Generic	BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle	2012-08-24 18:14:27 +00:00
Hexagon	Remove extra MayLoad/MayStore flags from atomic_load/store.	2012-08-28 03:11:32 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	Fix mips' long branch pass.	2012-08-28 03:03:05 +00:00
MSP430	Reapply r161633-161634 "Partition use lists so defs always come before uses.""	2012-08-10 00:21:30 +00:00
NVPTX	Add llvm.fabs intrinsic.	2012-05-28 21:48:37 +00:00
PowerPC	Reserve space for the mandatory traceback fields on PPC64.	2012-08-29 20:22:24 +00:00
SPARC	test/CodeGen/SPARC/private.ll: Fixup. Forgot to prune old RUN lines.	2012-07-03 04:29:20 +00:00
Thumb	Fix Thumb2 fixup kind in the integrated-as.	2012-09-01 15:06:36 +00:00
Thumb2	Add ADD and SUB to the predicable ARM instructions.	2012-08-16 23:21:55 +00:00
X86	Revert "Take account of boolean vector contents when promoting a build vector from i1 to some other type. rdar://problem/12210060"	2012-09-01 17:37:55 +00:00
XCore	Fix pattern for MKMSK instruction.	2012-06-13 17:59:12 +00:00