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c307b3034a
The VSX instruction definitions for lxsdx, lxvd2x, lxvdsx, and lxvw4x incorrectly use the XForm_1 instruction format, rather than the XX1Form instruction format. This is likely a pasto when creating these instructions, which were based on lvx and so forth. This patch uses the correct format. The existing reformatting test (test/MC/PowerPC/vsx.s) missed this because the two formats differ only in that XX1Form has an extension to the target register field in bit 31. The tests for these instructions used a target register of 7, so the default of 0 in bit 31 for XForm_1 didn't expose a problem. For register numbers 32-63 this would be noticeable. I've changed the test to use higher register numbers to verify my change is effective. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219416 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
deprecated-p7.s | ||
lcomm.s | ||
lit.local.cfg | ||
ppc32-ba.s | ||
ppc64-abiversion.s | ||
ppc64-encoding-4xx.s | ||
ppc64-encoding-6xx.s | ||
ppc64-encoding-bookII.s | ||
ppc64-encoding-bookIII.s | ||
ppc64-encoding-e500.s | ||
ppc64-encoding-ext.s | ||
ppc64-encoding-fp.s | ||
ppc64-encoding-spe.s | ||
ppc64-encoding-vmx.s | ||
ppc64-encoding.s | ||
ppc64-errors.s | ||
ppc64-fixup-apply.s | ||
ppc64-fixup-explicit.s | ||
ppc64-fixups.s | ||
ppc64-initial-cfa.s | ||
ppc64-localentry-error1.s | ||
ppc64-localentry-error2.s | ||
ppc64-localentry.s | ||
ppc64-operands.s | ||
ppc64-regs.s | ||
ppc64-relocs-01.s | ||
ppc64-tls-relocs-01.s | ||
ppc-llong.s | ||
ppc-machine.s | ||
ppc-nop.s | ||
ppc-reloc.s | ||
ppc-word.s | ||
tls-gd-obj.s | ||
tls-ie-obj.s | ||
tls-ld-obj.s | ||
vsx.s |