llvm-6502/lib/Target/Sparc
2006-03-28 13:48:33 +00:00
..
.cvsignore ignore generated files 2005-09-07 23:47:44 +00:00
DelaySlotFiller.cpp Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
FPMover.cpp Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
Makefile Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
README.txt Done 2006-02-09 20:00:19 +00:00
Sparc.h Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
Sparc.td Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
SparcAsmPrinter.cpp Add support for 'special' llvm globals like debug info and static ctors/dtors. 2006-03-09 06:14:35 +00:00
SparcInstrFormats.td Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
SparcInstrInfo.cpp Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
SparcInstrInfo.h Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
SparcInstrInfo.td The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter 2006-02-21 18:04:32 +00:00
SparcISelDAGToDAG.cpp SelectionDAGISel can now natively handle Switch instructions, in the same 2006-03-27 01:32:24 +00:00
SparcRegisterInfo.cpp Expose base register for DwarfWriter. Refactor code accordingly. 2006-03-28 13:48:33 +00:00
SparcRegisterInfo.h Expose base register for DwarfWriter. Refactor code accordingly. 2006-03-28 13:48:33 +00:00
SparcRegisterInfo.td D'oh - should be even numbered. 2006-03-24 22:48:02 +00:00
SparcSubtarget.cpp Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
SparcSubtarget.h Rename SPARC V8 target to be the LLVM SPARC target. 2006-02-05 05:50:24 +00:00
SparcTargetMachine.cpp Eliminate IntrinsicLowering from TargetMachine. 2006-03-23 05:43:16 +00:00
SparcTargetMachine.h Eliminate IntrinsicLowering from TargetMachine. 2006-03-23 05:43:16 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots