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https://github.com/c64scene-ar/llvm-6502.git
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fa49d7d6e4
There are two transforms in visitUrem that conflict with each other. *) One, if a divisor is a power of two, subtracts one from the divisor and turns it into a bitwise-and. *) The other unwraps both operands if they are surrounded by zext instructions. Flipping the order allows the subtraction to go beneath the sign extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181668 91177308-0d34-0410-b5e6-96231b3b80d8
152 lines
3.2 KiB
LLVM
152 lines
3.2 KiB
LLVM
; This test makes sure that urem instructions are properly eliminated.
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;
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; END.
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define i32 @test1(i32 %A) {
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; CHECK: @test1
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; CHECK-NEXT: ret i32 0
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%B = srem i32 %A, 1 ; ISA constant 0
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ret i32 %B
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}
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define i32 @test2(i32 %A) { ; 0 % X = 0, we don't need to preserve traps
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; CHECK: @test2
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; CHECK-NEXT: ret i32 0
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%B = srem i32 0, %A
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ret i32 %B
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}
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define i32 @test3(i32 %A) {
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; CHECK: @test3
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; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
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; CHECK-NEXT: ret i32 [[AND]]
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%B = urem i32 %A, 8
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ret i32 %B
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}
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define i1 @test3a(i32 %A) {
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; CHECK: @test3a
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; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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%B = srem i32 %A, -8
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%C = icmp ne i32 %B, 0
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ret i1 %C
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}
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define i32 @test4(i32 %X, i1 %C) {
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; CHECK: @test4
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; CHECK-NEXT: [[SEL:%.*]] = select i1 %C, i32 0, i32 7
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SEL]], %X
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%V = select i1 %C, i32 1, i32 8
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%R = urem i32 %X, %V
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ret i32 %R
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}
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define i32 @test5(i32 %X, i8 %B) {
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; CHECK: @test5
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 %B to i32
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; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 32, [[ZEXT]]
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %X
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; CHECK-NEXT: ret i32 [[AND]]
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%shift.upgrd.1 = zext i8 %B to i32
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%Amt = shl i32 32, %shift.upgrd.1
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%V = urem i32 %X, %Amt
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ret i32 %V
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}
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define i32 @test6(i32 %A) {
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; CHECK: @test6
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; CHECK-NEXT: ret i32 undef
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%B = srem i32 %A, 0 ;; undef
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ret i32 %B
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}
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define i32 @test7(i32 %A) {
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; CHECK: @test7
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; CHECK-NEXT: ret i32 0
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%B = mul i32 %A, 8
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%C = srem i32 %B, 4
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ret i32 %C
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}
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define i32 @test8(i32 %A) {
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; CHECK: @test8
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; CHECK-NEXT: ret i32 0
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%B = shl i32 %A, 4
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%C = srem i32 %B, 8
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ret i32 %C
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}
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define i32 @test9(i32 %A) {
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; CHECK: @test9
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; CHECK-NEXT: ret i32 0
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%B = mul i32 %A, 64
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%C = urem i32 %B, 32
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ret i32 %C
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}
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define i32 @test10(i8 %c) {
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; CHECK: @test10
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; CHECK-NEXT: ret i32 0
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%tmp.1 = zext i8 %c to i32
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%tmp.2 = mul i32 %tmp.1, 4
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%tmp.3 = sext i32 %tmp.2 to i64
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%tmp.5 = urem i64 %tmp.3, 4
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%tmp.6 = trunc i64 %tmp.5 to i32
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ret i32 %tmp.6
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}
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define i32 @test11(i32 %i) {
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; CHECK: @test11
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; CHECK-NEXT: ret i32 0
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%tmp.1 = and i32 %i, -2
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%tmp.3 = mul i32 %tmp.1, 2
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%tmp.5 = urem i32 %tmp.3, 4
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ret i32 %tmp.5
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}
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define i32 @test12(i32 %i) {
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; CHECK: @test12
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; CHECK-NEXT: ret i32 0
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%tmp.1 = and i32 %i, -4
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%tmp.5 = srem i32 %tmp.1, 2
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ret i32 %tmp.5
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}
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define i32 @test13(i32 %i) {
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; CHECK: @test13
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; CHECK-NEXT: ret i32 0
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%x = srem i32 %i, %i
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ret i32 %x
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}
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define i64 @test14(i64 %x, i32 %y) {
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; CHECK: @test14
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %y
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add i64 [[ZEXT]], -1
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; CHECK-NEXT: [[AND:%.*]] = and i64 [[ADD]], %x
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; CHECK-NEXT: ret i64 [[AND]]
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%shl = shl i32 1, %y
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%zext = zext i32 %shl to i64
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%urem = urem i64 %x, %zext
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ret i64 %urem
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}
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define i64 @test15(i32 %x, i32 %y) {
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; CHECK: @test15
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; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, %y
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %x
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[AND]] to i64
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; CHECK-NEXT: ret i64 [[ZEXT]]
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%shl = shl i32 1, %y
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%zext0 = zext i32 %shl to i64
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%zext1 = zext i32 %x to i64
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%urem = urem i64 %zext1, %zext0
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ret i64 %urem
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}
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