llvm-6502/lib/Target/Sparc
Bill Wendling 587daedce2 Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13 21:33:08 +00:00
..
AsmPrinter Rename PaddedSize to AllocSize, in the hope that this 2009-05-09 07:06:46 +00:00
CMakeLists.txt CMake: corrected split of Alpha and Sparc AsmPrinters. 2008-11-11 17:10:13 +00:00
DelaySlotFiller.cpp Remove non-DebugLoc versions of buildMI from Sparc. 2009-02-13 02:31:35 +00:00
FPMover.cpp Add explicit keywords. 2009-02-18 16:37:45 +00:00
Makefile Removed trailing whitespace from Makefiles. 2009-01-09 16:44:42 +00:00
README.txt
Sparc.h Instead of passing in an unsigned value for the optimization level, use an enum, 2009-04-29 23:29:43 +00:00
Sparc.td Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files. 2008-11-24 07:34:46 +00:00
SparcCallingConv.td Fix a thinko and unbreak sparc default CC 2008-10-10 21:47:37 +00:00
SparcInstrFormats.td
SparcInstrInfo.cpp Change MachineInstrBuilder::addReg() to take a flag instead of a list of 2009-05-13 21:33:08 +00:00
SparcInstrInfo.h Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 2009-01-20 19:12:24 +00:00
SparcInstrInfo.td Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as 2008-10-11 22:08:30 +00:00
SparcISelDAGToDAG.cpp Eliminate remaining non-DebugLoc version of getTargetNode. 2009-02-06 19:16:40 +00:00
SparcISelLowering.cpp Remove non-DebugLoc versions of buildMI from Sparc. 2009-02-13 02:31:35 +00:00
SparcISelLowering.h Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing 2009-02-07 16:15:20 +00:00
SparcRegisterInfo.cpp Propagate debug loc info through prologue/epilogue. 2009-02-23 00:42:30 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetAsmInfo.cpp Add interface for section override. Use this for Sparc, since it should use named BSS section. 2008-08-16 12:58:12 +00:00
SparcTargetAsmInfo.h Reduce heap trashing due to std::string construction / concatenation via caching of section flags string representations 2008-08-16 12:57:07 +00:00
SparcTargetMachine.cpp Instead of passing in an unsigned value for the optimization level, use an enum, 2009-04-29 23:29:43 +00:00
SparcTargetMachine.h Instead of passing in an unsigned value for the optimization level, use an enum, 2009-04-29 23:29:43 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots