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6410552250
a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
2.1 KiB
C++
59 lines
2.1 KiB
C++
//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetInstrInfoImpl class, it just provides default
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// implementations of various methods.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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using namespace llvm;
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// commuteInstruction - The default implementation of this method just exchanges
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// operand 1 and 2.
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MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
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assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
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"This only knows how to commute register operands so far");
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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bool Reg1IsKill = MI->getOperand(1).isKill();
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bool Reg2IsKill = MI->getOperand(2).isKill();
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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MI->getOperand(2).setIsKill(Reg1IsKill);
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MI->getOperand(1).setIsKill(Reg2IsKill);
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return MI;
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}
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bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
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const std::vector<MachineOperand> &Pred) const {
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bool MadeChange = false;
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const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
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if (TID->Flags & M_PREDICABLE) {
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for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg()) {
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MO.setReg(Pred[j].getReg());
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MadeChange = true;
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} else if (MO.isImm()) {
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MO.setImm(Pred[j].getImm());
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MadeChange = true;
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} else if (MO.isMBB()) {
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MO.setMBB(Pred[j].getMBB());
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MadeChange = true;
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}
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++j;
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}
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}
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}
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return MadeChange;
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}
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