Andrew Trick e02a1501e7 Combine thumb2-ror tests. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130498 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-29 14:02:41 +00:00
..
Alpha
ARM	Revert r130454; apparently this doesn't actually work.	2011-04-28 23:55:14 +00:00
Blackfin
CBackend
CellSPU	don't test for codegen of 'store undef'	2011-04-09 02:31:26 +00:00
CPP
Generic	Un-XFAIL this test for ARM. <rdar://problem/7662569>	2011-04-20 21:47:45 +00:00
MBlaze	Add scheduling information for the MBlaze backend.	2011-04-11 22:31:52 +00:00
Mips	Lower BlockAddress node when relocation-model is static.	2011-04-25 17:10:45 +00:00
MSP430
PowerPC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
PTX	PTX: support for bitwise operations on predicates	2011-04-28 00:19:51 +00:00
SPARC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
SystemZ
Thumb	Be careful about scheduling nodes above previous calls. It increase usages of	2011-04-26 21:31:35 +00:00
Thumb2	Combine thumb2-ror tests.	2011-04-29 14:02:41 +00:00
X86	fast-isel sret calls, try 2. We actually do need to do something on x86-32. rdar://problem/9303592 .	2011-04-28 20:19:12 +00:00
XCore