mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 04:29:44 +00:00
ebd4eec538
The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused it to corrupt the encoding of that by clobbering the first operand with the second one. Undo that damage and only apply the SMRD logic to that. Fixes some derivates related piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188558 91177308-0d34-0410-b5e6-96231b3b80d8
457 lines
9.7 KiB
TableGen
457 lines
9.7 KiB
TableGen
//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// SI Instruction format definitions.
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//
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//===----------------------------------------------------------------------===//
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class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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AMDGPUInst<outs, ins, asm, pattern> {
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field bits<1> VM_CNT = 0;
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field bits<1> EXP_CNT = 0;
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field bits<1> LGKM_CNT = 0;
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field bits<1> MIMG = 0;
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field bits<1> SMRD = 0;
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let TSFlags{0} = VM_CNT;
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let TSFlags{1} = EXP_CNT;
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let TSFlags{2} = LGKM_CNT;
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let TSFlags{3} = MIMG;
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let TSFlags{4} = SMRD;
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}
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class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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field bits<32> Inst;
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let Size = 4;
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}
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class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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field bits<64> Inst;
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let Size = 8;
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}
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//===----------------------------------------------------------------------===//
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// Scalar operations
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//===----------------------------------------------------------------------===//
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class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32<outs, ins, asm, pattern> {
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bits<7> SDST;
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bits<8> SSRC0;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = op;
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let Inst{22-16} = SDST;
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let Inst{31-23} = 0x17d; //encoding;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32 <outs, ins, asm, pattern> {
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bits<7> SDST;
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bits<8> SSRC0;
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bits<8> SSRC1;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = SSRC1;
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let Inst{22-16} = SDST;
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let Inst{29-23} = op;
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let Inst{31-30} = 0x2; // encoding
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32<outs, ins, asm, pattern> {
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bits<8> SSRC0;
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bits<8> SSRC1;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = SSRC1;
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let Inst{22-16} = op;
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let Inst{31-23} = 0x17e;
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let DisableEncoding = "$dst";
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32 <outs, ins , asm, pattern> {
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bits <7> SDST;
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bits <16> SIMM16;
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let Inst{15-0} = SIMM16;
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let Inst{22-16} = SDST;
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let Inst{27-23} = op;
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let Inst{31-28} = 0xb; //encoding
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
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(outs),
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ins,
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asm,
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pattern > {
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bits <16> SIMM16;
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let Inst{15-0} = SIMM16;
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let Inst{22-16} = op;
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let Inst{31-23} = 0x17f; // encoding
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
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list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
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bits<7> SDST;
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bits<7> SBASE;
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bits<8> OFFSET;
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let Inst{7-0} = OFFSET;
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let Inst{8} = imm;
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let Inst{14-9} = SBASE{6-1};
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let Inst{21-15} = SDST;
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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let LGKM_CNT = 1;
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let SMRD = 1;
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}
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//===----------------------------------------------------------------------===//
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// Vector ALU operations
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//===----------------------------------------------------------------------===//
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let Uses = [EXEC] in {
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class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32 <outs, ins, asm, pattern> {
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bits<8> VDST;
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bits<9> SRC0;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = op;
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let Inst{24-17} = VDST;
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let Inst{31-25} = 0x3f; //encoding
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32 <outs, ins, asm, pattern> {
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bits<8> VDST;
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bits<9> SRC0;
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bits<8> VSRC1;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = VSRC1;
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let Inst{24-17} = VDST;
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let Inst{30-25} = op;
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let Inst{31} = 0x0; //encoding
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64 <outs, ins, asm, pattern> {
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bits<8> dst;
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bits<9> src0;
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bits<9> src1;
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bits<9> src2;
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bits<3> abs;
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bits<1> clamp;
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bits<2> omod;
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bits<3> neg;
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let Inst{7-0} = dst;
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let Inst{10-8} = abs;
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let Inst{11} = clamp;
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let Inst{25-17} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = src0;
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let Inst{49-41} = src1;
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let Inst{58-50} = src2;
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let Inst{60-59} = omod;
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let Inst{63-61} = neg;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64 <outs, ins, asm, pattern> {
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bits<8> dst;
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bits<9> src0;
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bits<9> src1;
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bits<9> src2;
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bits<7> sdst;
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bits<2> omod;
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bits<3> neg;
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let Inst{7-0} = dst;
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let Inst{14-8} = sdst;
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let Inst{25-17} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = src0;
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let Inst{49-41} = src1;
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let Inst{58-50} = src2;
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let Inst{60-59} = omod;
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let Inst{63-61} = neg;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
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Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
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bits<9> SRC0;
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bits<8> VSRC1;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = VSRC1;
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let Inst{24-17} = op;
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let Inst{31-25} = 0x3e;
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let DisableEncoding = "$dst";
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32 <outs, ins, asm, pattern> {
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bits<8> VDST;
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bits<8> VSRC;
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bits<2> ATTRCHAN;
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bits<6> ATTR;
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let Inst{7-0} = VSRC;
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let Inst{9-8} = ATTRCHAN;
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let Inst{15-10} = ATTR;
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let Inst{17-16} = op;
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let Inst{25-18} = VDST;
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let Inst{31-26} = 0x32; // encoding
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let neverHasSideEffects = 1;
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let mayLoad = 1;
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let mayStore = 0;
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}
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} // End Uses = [EXEC]
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//===----------------------------------------------------------------------===//
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// Vector I/O operations
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//===----------------------------------------------------------------------===//
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let Uses = [EXEC] in {
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class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64 <outs, ins, asm, pattern> {
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bits<8> vdst;
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bits<1> gds;
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bits<8> addr;
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bits<8> data0;
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bits<8> data1;
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bits<8> offset0;
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bits<8> offset1;
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let Inst{7-0} = offset0;
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let Inst{15-8} = offset1;
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let Inst{17} = gds;
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let Inst{25-18} = op;
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let Inst{31-26} = 0x36; //encoding
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let Inst{39-32} = addr;
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let Inst{47-40} = data0;
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let Inst{55-48} = data1;
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let Inst{63-56} = vdst;
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let LGKM_CNT = 1;
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}
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class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64<outs, ins, asm, pattern> {
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bits<12> offset;
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bits<1> offen;
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bits<1> idxen;
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bits<1> glc;
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bits<1> addr64;
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bits<1> lds;
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bits<8> vaddr;
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bits<8> vdata;
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bits<7> srsrc;
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bits<1> slc;
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bits<1> tfe;
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bits<8> soffset;
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let Inst{11-0} = offset;
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let Inst{12} = offen;
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let Inst{13} = idxen;
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let Inst{14} = glc;
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let Inst{15} = addr64;
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let Inst{16} = lds;
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let Inst{24-18} = op;
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let Inst{31-26} = 0x38; //encoding
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let Inst{39-32} = vaddr;
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let Inst{47-40} = vdata;
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let Inst{52-48} = srsrc{6-2};
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let Inst{54} = slc;
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let Inst{55} = tfe;
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let Inst{63-56} = soffset;
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let VM_CNT = 1;
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let EXP_CNT = 1;
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let neverHasSideEffects = 1;
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}
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class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64<outs, ins, asm, pattern> {
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bits<8> VDATA;
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bits<12> OFFSET;
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bits<1> OFFEN;
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bits<1> IDXEN;
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bits<1> GLC;
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bits<1> ADDR64;
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bits<4> DFMT;
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bits<3> NFMT;
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bits<8> VADDR;
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bits<7> SRSRC;
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bits<1> SLC;
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bits<1> TFE;
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bits<8> SOFFSET;
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let Inst{11-0} = OFFSET;
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let Inst{12} = OFFEN;
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let Inst{13} = IDXEN;
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let Inst{14} = GLC;
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let Inst{15} = ADDR64;
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let Inst{18-16} = op;
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let Inst{22-19} = DFMT;
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let Inst{25-23} = NFMT;
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let Inst{31-26} = 0x3a; //encoding
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let Inst{39-32} = VADDR;
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let Inst{47-40} = VDATA;
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let Inst{52-48} = SRSRC{6-2};
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let Inst{54} = SLC;
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let Inst{55} = TFE;
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let Inst{63-56} = SOFFSET;
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let VM_CNT = 1;
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let EXP_CNT = 1;
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let neverHasSideEffects = 1;
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}
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class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64 <outs, ins, asm, pattern> {
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bits<8> VDATA;
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bits<4> DMASK;
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bits<1> UNORM;
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bits<1> GLC;
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bits<1> DA;
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bits<1> R128;
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bits<1> TFE;
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bits<1> LWE;
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bits<1> SLC;
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bits<8> VADDR;
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bits<7> SRSRC;
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bits<7> SSAMP;
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let Inst{11-8} = DMASK;
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let Inst{12} = UNORM;
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let Inst{13} = GLC;
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let Inst{14} = DA;
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let Inst{15} = R128;
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let Inst{16} = TFE;
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let Inst{17} = LWE;
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let Inst{24-18} = op;
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let Inst{25} = SLC;
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let Inst{31-26} = 0x3c;
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let Inst{39-32} = VADDR;
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let Inst{47-40} = VDATA;
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let Inst{52-48} = SRSRC{6-2};
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let Inst{57-53} = SSAMP{6-2};
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let VM_CNT = 1;
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let EXP_CNT = 1;
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let MIMG = 1;
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}
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def EXP : Enc64<
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(outs),
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(ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
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VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
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"EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
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[] > {
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bits<4> EN;
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bits<6> TGT;
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bits<1> COMPR;
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bits<1> DONE;
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bits<1> VM;
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bits<8> VSRC0;
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bits<8> VSRC1;
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bits<8> VSRC2;
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bits<8> VSRC3;
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let Inst{3-0} = EN;
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let Inst{9-4} = TGT;
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let Inst{10} = COMPR;
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let Inst{11} = DONE;
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let Inst{12} = VM;
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let Inst{31-26} = 0x3e;
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let Inst{39-32} = VSRC0;
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let Inst{47-40} = VSRC1;
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let Inst{55-48} = VSRC2;
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let Inst{63-56} = VSRC3;
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let EXP_CNT = 1;
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}
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} // End Uses = [EXEC]
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