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https://github.com/c64scene-ar/llvm-6502.git
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ebd4eec538
The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused it to corrupt the encoding of that by clobbering the first operand with the second one. Undo that damage and only apply the SMRD logic to that. Fixes some derivates related piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188558 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
3.2 KiB
C++
100 lines
3.2 KiB
C++
//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SIINSTRINFO_H
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#define SIINSTRINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "SIRegisterInfo.h"
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namespace llvm {
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class SIInstrInfo : public AMDGPUInstrInfo {
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private:
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const SIRegisterInfo RI;
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public:
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explicit SIInstrInfo(AMDGPUTargetMachine &tm);
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const SIRegisterInfo &getRegisterInfo() const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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unsigned commuteOpcode(unsigned Opcode) const;
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virtual MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI=false) const;
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virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const;
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virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
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virtual bool isMov(unsigned Opcode) const;
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virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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int isMIMG(uint16_t Opcode) const;
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int isSMRD(uint16_t Opcode) const;
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virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
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virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
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virtual unsigned calculateIndirectAddress(unsigned RegIndex,
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unsigned Channel) const;
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virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
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unsigned SourceReg) const;
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virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
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virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const;
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virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const;
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virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
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};
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namespace AMDGPU {
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int getVOPe64(uint16_t Opcode);
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int getCommuteRev(uint16_t Opcode);
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int getCommuteOrig(uint16_t Opcode);
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} // End namespace AMDGPU
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} // End namespace llvm
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namespace SIInstrFlags {
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enum Flags {
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// First 4 bits are the instruction encoding
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VM_CNT = 1 << 0,
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EXP_CNT = 1 << 1,
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LGKM_CNT = 1 << 2
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};
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}
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#endif //SIINSTRINFO_H
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