Bradley Smith a493b7786a [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-09 14:42:11 +00:00
..
Analysis	Delinearize: Extend informationin -analyze output	2014-04-09 07:53:49 +00:00
AsmParser
Bitcode
CodeGen	WinCOFF: Emit common symbols as specified in the COFF spec	2014-04-08 22:33:40 +00:00
DebugInfo
ExecutionEngine	Changes in IntelJITEventListener - By Arch Robinson	2014-04-06 11:08:33 +00:00
IR	[C++11] More 'nullptr' conversion or in some cases just using a boolean check instead of comparing to nullptr.	2014-04-09 06:08:46 +00:00
IRReader
LineEditor
Linker
LTO
MC	WinCOFF: Emit common symbols as specified in the COFF spec	2014-04-08 22:33:40 +00:00
Object	Object: add type names for ARM/COFF relocations	2014-04-09 06:18:28 +00:00
Option
ProfileData
Support	Revert "YAMLIO: Encode ambiguous hex strings explicitly"	2014-04-09 14:35:17 +00:00
TableGen	[C++11] Make use of 'nullptr' in TableGen library.	2014-04-09 04:50:04 +00:00
Target	[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.	2014-04-09 14:42:11 +00:00
Transforms	SLPVectorizer: Only vectorize intrinsics whose operands are widened equally	2014-04-09 14:20:47 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile