mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a51752cbea
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75926 91177308-0d34-0410-b5e6-96231b3b80d8
230 lines
8.4 KiB
C++
230 lines
8.4 KiB
C++
//===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SystemZTargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "systemz-lower"
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#include "SystemZISelLowering.h"
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#include "SystemZ.h"
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#include "SystemZTargetMachine.h"
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#include "SystemZSubtarget.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/GlobalAlias.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/VectorExtras.h"
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using namespace llvm;
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SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
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// Set up the register classes.
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addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
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addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
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// Compute derived properties from the register classes
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computeRegisterProperties();
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// Provide all sorts of operation actions
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setStackPointerRegisterToSaveRestore(SystemZ::R15D);
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setSchedulingPreference(SchedulingForLatency);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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}
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SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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default:
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assert(0 && "unimplemented operand");
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return SDValue();
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}
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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#include "SystemZGenCallingConv.inc"
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SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
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SelectionDAG &DAG) {
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unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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switch (CC) {
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default:
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assert(0 && "Unsupported calling convention");
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case CallingConv::C:
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case CallingConv::Fast:
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return LowerCCCArguments(Op, DAG);
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}
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}
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/// LowerCCCArguments - transform physical registers into virtual registers and
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/// generate load operations for arguments places on the stack.
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// FIXME: struct return stuff
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// FIXME: varargs
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SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
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SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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SDValue Root = Op.getOperand(0);
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
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unsigned CC = MF.getFunction()->getCallingConv();
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DebugLoc dl = Op.getDebugLoc();
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
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CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
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assert(!isVarArg && "Varargs not supported yet");
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SmallVector<SDValue, 16> ArgValues;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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if (VA.isRegLoc()) {
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// Arguments passed in registers
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MVT RegVT = VA.getLocVT();
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switch (RegVT.getSimpleVT()) {
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default:
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cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
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<< RegVT.getSimpleVT()
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<< "\n";
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abort();
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case MVT::i64:
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unsigned VReg =
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RegInfo.createVirtualRegister(SystemZ::GR64RegisterClass);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
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// If this is an 8/16/32-bit value, it is really passed promoted to 64
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
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ArgValues.push_back(ArgValue);
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}
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} else {
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// Sanity check
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assert(VA.isMemLoc());
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// Load the argument to a virtual register
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unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
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if (ObjSize > 8) {
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cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
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<< VA.getLocVT().getSimpleVT()
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<< "\n";
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}
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
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ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
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PseudoSourceValue::getFixedStack(FI), 0));
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}
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}
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ArgValues.push_back(Root);
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// Return the new list of results.
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return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
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&ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
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}
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SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
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// CCValAssign - represent the assignment of the return value to a location
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SmallVector<CCValAssign, 16> RVLocs;
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unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
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bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
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DebugLoc dl = Op.getDebugLoc();
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
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// Analize return values of ISD::RET
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CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
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// If this is the first return lowered for this function, add the regs to the
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// liveout set for the function.
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if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
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for (unsigned i = 0; i != RVLocs.size(); ++i)
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if (RVLocs[i].isRegLoc())
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DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
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}
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// The chain is always operand #0
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SDValue Chain = Op.getOperand(0);
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SDValue Flag;
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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SDValue ResValue = Op.getOperand(i*2+1);
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assert(VA.isRegLoc() && "Can only return in registers!");
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// If this is an 8/16/32-bit value, it is really should be passed promoted
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// to 64 bits.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
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else if (VA.getLocInfo() == CCValAssign::AExt)
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ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
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// ISD::RET => ret chain, (regnum1,val1), ...
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// So i*2+1 index only the regnums
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad.
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Flag = Chain.getValue(1);
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}
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if (Flag.getNode())
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return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
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// Return Void
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return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
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}
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const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
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default: return NULL;
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}
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}
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