mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-04 06:09:05 +00:00
3185f9a2ea
on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163010 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.4 KiB
LLVM
58 lines
1.4 KiB
LLVM
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -mattr=n64 %s -o - \
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; RUN: | llvm-objdump -disassemble -triple mips64el -mattr +mips64r2 - \
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; RUN: | FileCheck %s
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define i64 @dext(i64 %i) nounwind readnone {
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entry:
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; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
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%shr = lshr i64 %i, 5
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%and = and i64 %shr, 1023
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ret i64 %and
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}
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define i64 @dextu(i64 %i) nounwind readnone {
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entry:
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; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 2, 6
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%shr = lshr i64 %i, 34
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%and = and i64 %shr, 63
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ret i64 %and
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}
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define i64 @dextm(i64 %i) nounwind readnone {
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entry:
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; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 2
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%shr = lshr i64 %i, 5
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%and = and i64 %shr, 17179869183
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ret i64 %and
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}
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define i64 @dins(i64 %i, i64 %j) nounwind readnone {
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entry:
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; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
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%shl2 = shl i64 %j, 8
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%and = and i64 %shl2, 261888
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%and3 = and i64 %i, -261889
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%or = or i64 %and3, %and
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ret i64 %or
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}
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define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
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entry:
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; CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 10, 1
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%shl4 = shl i64 %j, 10
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%and = and i64 %shl4, 8796093021184
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%and5 = and i64 %i, -8796093021185
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%or = or i64 %and5, %and
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ret i64 %or
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}
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define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
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entry:
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; CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 8, 13
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%shl4 = shl i64 %j, 40
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%and = and i64 %shl4, 9006099743113216
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%and5 = and i64 %i, -9006099743113217
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%or = or i64 %and5, %and
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ret i64 %or
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}
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