llvm-6502/test/CodeGen
Andrew Trick 4e1fb18940 MIsched: Improve the interface to SchedDFS analysis (subtrees).
Allow the strategy to select SchedDFS. Allow the results of SchedDFS
to affect initialization of the scheduler state.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 06:33:57 +00:00
..
ARM Remove some register allocation order dependencies. 2013-01-19 00:03:32 +00:00
CPP
Generic For inline asm: 2013-01-11 18:12:39 +00:00
Hexagon Add indexed load/store instructions for offset validation check. 2013-01-17 18:42:37 +00:00
MBlaze
Mips [mips] Set flag neverHasSideEffects flag on some of the floating point instructions. 2013-01-25 00:20:39 +00:00
MSP430
NVPTX [NVPTX] Fix crash with unnamed struct arguments 2012-12-05 20:50:28 +00:00
PowerPC Restore reverted test case, this time with REQUIRES: asserts 2013-01-17 19:46:51 +00:00
R600 DAGCombiner: Avoid generating illegal vector INT_TO_FP nodes 2013-01-02 22:13:01 +00:00
SI Add R600 backend 2012-12-11 21:25:42 +00:00
SPARC
Thumb
Thumb2 Remove some register allocation order dependencies. 2013-01-19 00:03:32 +00:00
X86 MIsched: Improve the interface to SchedDFS analysis (subtrees). 2013-01-25 06:33:57 +00:00
XCore