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https://github.com/c64scene-ar/llvm-6502.git
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1c49fda408
try to reduce the width of this load, and would end up transforming: (truncate (lshr (sextload i48 <ptr> as i64), 32) to i32) to (truncate (zextload i32 <ptr+4> as i64) to i32) We lost the sext attached to the load while building the narrower i32 load, and replaced it with a zext because lshr always zext's the results. Instead, bail out of this combine when there is a conflict between a sextload and a zext narrowing. The rest of the DAG combiner still optimize the code down to the proper single instruction: movswl 6(...),%eax Which is exactly what we wanted. Previously we read past the end *and* missed the sign extension: movl 6(...), %eax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169802 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
884 B
LLVM
31 lines
884 B
LLVM
; RUN: llc < %s -march=x86 | FileCheck %s
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; When doing sign extension, use the sext-load lowering to take advantage of
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; x86's sign extension during loads.
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;
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; CHECK: test1:
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; CHECK: movsbl {{.*}}, %eax
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; CHECK-NEXT: ret
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define i32 @test1(i32 %X) nounwind {
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entry:
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%tmp12 = trunc i32 %X to i8 ; <i8> [#uses=1]
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%tmp123 = sext i8 %tmp12 to i32 ; <i32> [#uses=1]
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ret i32 %tmp123
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}
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; When using a sextload representation, ensure that the sign extension is
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; preserved even when removing shifted-out low bits.
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;
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; CHECK: test2:
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; CHECK: movswl {{.*}}, %eax
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; CHECK-NEXT: ret
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define i32 @test2({i16, [6 x i8]}* %this) {
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entry:
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%b48 = getelementptr inbounds { i16, [6 x i8] }* %this, i32 0, i32 1
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%cast = bitcast [6 x i8]* %b48 to i48*
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%bf.load = load i48* %cast, align 2
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%bf.ashr = ashr i48 %bf.load, 32
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%bf.cast = trunc i48 %bf.ashr to i32
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ret i32 %bf.cast
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}
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