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Newer POWER cores, and the A2, support the cmpb instruction. This instruction compares its operands, treating each of the 8 bytes in the GPRs separately, returning a 'mask' result of 0 (for false) or -1 (for true) in each byte. Code generation support is added, in the form of a PPCISelDAGToDAG DAG-preprocessing routine, that recognizes patterns close to what the instruction computes (either exactly, or related by a constant masking operation), and generates the cmpb instruction (along with any necessary constant masking operation). This can be expanded if use cases arise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225106 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
lit.local.cfg | ||
ppc64-encoding-4xx.txt | ||
ppc64-encoding-6xx.txt | ||
ppc64-encoding-bookII.txt | ||
ppc64-encoding-bookIII.txt | ||
ppc64-encoding-e500.txt | ||
ppc64-encoding-ext.txt | ||
ppc64-encoding-fp.txt | ||
ppc64-encoding-vmx.txt | ||
ppc64-encoding.txt | ||
ppc64-operands.txt | ||
vsx.txt |