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Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
3.2 KiB
LLVM
93 lines
3.2 KiB
LLVM
; RUN: llc < %s -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs -mtriple=x86_64-apple-darwin10
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; <rdar://problem/7755473>
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; PR12821
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%0 = type { i32, i8*, i8*, %1*, i8*, i64, i64, i32, i32, i32, i32, [1024 x i8] }
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%1 = type { i8*, i32, i32, i16, i16, %2, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %2, %3*, i32, [3 x i8], [1 x i8], %2, i32, i64 }
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%2 = type { i8*, i32 }
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%3 = type opaque
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declare fastcc i32 @func(%0*, i32, i32) nounwind ssp
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define fastcc void @func2(%0* %arg, i32 %arg1) nounwind ssp {
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bb:
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br label %.exit3
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.exit3: ; preds = %.exit3, %bb
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switch i32 undef, label %.exit3 [
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i32 -1, label %.loopexit
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i32 37, label %bb2
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]
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bb2: ; preds = %bb5, %bb3, %.exit3
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br i1 undef, label %bb3, label %bb5
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bb3: ; preds = %bb2
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switch i32 undef, label %infloop [
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i32 125, label %.loopexit
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i32 -1, label %bb4
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i32 37, label %bb2
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]
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bb4: ; preds = %bb3
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%tmp = add nsw i32 undef, 1 ; <i32> [#uses=1]
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br label %.loopexit
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bb5: ; preds = %bb2
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switch i32 undef, label %infloop1 [
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i32 -1, label %.loopexit
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i32 37, label %bb2
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]
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.loopexit: ; preds = %bb5, %bb4, %bb3, %.exit3
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%.04 = phi i32 [ %tmp, %bb4 ], [ undef, %bb3 ], [ undef, %.exit3 ], [ undef, %bb5 ] ; <i32> [#uses=2]
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br i1 undef, label %bb8, label %bb6
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bb6: ; preds = %.loopexit
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%tmp7 = tail call fastcc i32 @func(%0* %arg, i32 %.04, i32 undef) nounwind ssp ; <i32> [#uses=0]
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ret void
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bb8: ; preds = %.loopexit
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%tmp9 = sext i32 %.04 to i64 ; <i64> [#uses=1]
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%tmp10 = getelementptr inbounds %0, %0* %arg, i64 0, i32 11, i64 %tmp9 ; <i8*> [#uses=1]
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store i8 0, i8* %tmp10, align 1
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ret void
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infloop: ; preds = %infloop, %bb3
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br label %infloop
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infloop1: ; preds = %infloop1, %bb5
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br label %infloop1
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}
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; RAFast would forget to add a super-register <imp-def> when rewriting:
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; %vreg10:sub_32bit<def,read-undef> = COPY %R9D<kill>
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; This trips up the machine code verifier.
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define void @autogen_SD24657(i8*, i32*, i64*, i32, i64, i8) {
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BB:
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%A4 = alloca <16 x i16>
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%A3 = alloca double
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%A2 = alloca <2 x i8>
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%A1 = alloca i1
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%A = alloca i32
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%L = load i8, i8* %0
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store i8 -37, i8* %0
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%E = extractelement <4 x i64> zeroinitializer, i32 2
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%Shuff = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 5, i32 7, i32 1, i32 3>
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%I = insertelement <2 x i8> <i8 -1, i8 -1>, i8 %5, i32 1
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%B = fadd float 0x45CDF5B1C0000000, 0x45CDF5B1C0000000
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%FC = uitofp i32 275048 to double
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%Sl = select i1 true, <2 x i8> %I, <2 x i8> <i8 -1, i8 -1>
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%Cmp = icmp slt i64 0, %E
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br label %CF
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CF: ; preds = %BB
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store i8 %5, i8* %0
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store <2 x i8> %I, <2 x i8>* %A2
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store i8 %5, i8* %0
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store i8 %5, i8* %0
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store i8 %5, i8* %0
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ret void
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}
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