llvm-6502/test/MC/ARM/thumb2-exception-return-mclass.s
Oliver Stannard e7c9c44387 [Thumb2] RFE, SRS and "SUBS pc, lr" are undefined on v7M
These instructions are related to the v7[AR] exception model, and are
not defined on v7M.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-20 15:37:35 +00:00

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ArmAsm

# RUN: not llvm-mc -triple thumbv7m -assemble < %s 2>&1 | FileCheck %s
.text
# CHECK: instruction requires: !armv*m
# CHECK-NEXT: srsdb sp, #7
srsdb sp, #7
# CHECK: instruction requires: !armv*m
# CHECK-NEXT: rfeia r6
rfeia r6
# CHECK: instruction requires: !armv*m
# CHECK-NEXT: subs pc, lr, #42
subs pc, lr, #42