llvm-6502/lib/CodeGen
2011-01-13 19:27:50 +00:00
..
AsmPrinter Appropriately truncate debug info range in dwarf output. 2011-01-11 21:42:10 +00:00
SelectionDAG Fix r123346 to handle scalar types too. 2011-01-13 01:06:51 +00:00
AggressiveAntiDepBreaker.cpp Simplify AggressiveAntiDepBreaker's use of register aliases. 2010-12-14 23:23:15 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
AllocationOrder.h Add an AllocationOrder class that can iterate over the allocatable physical 2010-12-10 18:36:02 +00:00
Analysis.cpp Enable sibling call optimization of libcalls which are expanded during 2010-11-30 23:55:39 +00:00
AntiDepBreaker.h
BranchFolding.cpp
BranchFolding.h
CalcSpillWeights.cpp Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance. 2011-01-09 03:05:53 +00:00
CallingConvLower.cpp Simplify CCState's use of register aliases. 2010-12-14 23:28:01 +00:00
CMakeLists.txt sort this. 2011-01-09 21:31:39 +00:00
CodeGen.cpp Stub out a new LiveDebugVariables pass. 2010-11-30 02:17:10 +00:00
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
DwarfEHPrepare.cpp
EdgeBundles.cpp Add a hidden command line option to display edge bundle graphs as they are 2011-01-05 21:50:24 +00:00
ELF.h Merge System into Support. 2010-11-29 18:16:10 +00:00
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp Fixed version of 121434 with no new memory leaks. 2010-12-10 07:39:47 +00:00
ELFWriter.h
ExpandISelPseudos.cpp Rename ExpandPseudos to ExpandISelPseudos to help clarify its role. 2010-11-18 18:45:06 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
IfConversion.cpp
InlineSpiller.cpp Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual and 2011-01-09 21:17:37 +00:00
IntrinsicLowering.cpp Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call. 2011-01-08 01:24:27 +00:00
LatencyPriorityQueue.cpp Various bits of framework needed for precise machine-level selection 2010-12-24 05:03:26 +00:00
LiveDebugVariables.cpp Try again enabling LiveDebugVariables. 2011-01-12 23:36:21 +00:00
LiveDebugVariables.h Emit DBG_VALUE instructions from LiveDebugVariables. 2010-12-03 21:47:10 +00:00
LiveInterval.cpp Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual and 2011-01-09 21:17:37 +00:00
LiveIntervalAnalysis.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
LiveIntervalUnion.cpp Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance. 2011-01-09 03:05:53 +00:00
LiveIntervalUnion.h Provide LiveIntervalUnion::Query::checkLoopInterference. 2010-12-17 04:09:47 +00:00
LiveRangeEdit.cpp
LiveRangeEdit.h Teach the inline spiller to attempt folding a load instruction into its single 2010-12-18 03:04:14 +00:00
LiveStackAnalysis.cpp Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual and 2011-01-09 21:17:37 +00:00
LiveVariables.cpp Use an IndexedMap for LiveVariables::VirtRegInfo. 2011-01-08 23:10:57 +00:00
LLVMTargetMachine.cpp Pass a Banner argument to the machine code verifier both from 2010-12-18 00:06:56 +00:00
LocalStackSlotAllocation.cpp Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
LowerSubregs.cpp
MachineBasicBlock.cpp Speculatively revert r123384 to make llvm-gcc-i386-linux-selfhost buildbot happy. 2011-01-13 19:27:50 +00:00
MachineCSE.cpp fit in 80 cols and use MBB::isSuccessor instead of a hand 2011-01-10 07:51:31 +00:00
MachineDominators.cpp
MachineFunction.cpp Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
MachineFunctionAnalysis.cpp Clean up a funky pass registration that got passed over when I got rid of static constructors. 2011-01-04 00:55:21 +00:00
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
MachineLICM.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
MachineLoopInfo.cpp
MachineLoopRanges.cpp Add MachineLoopRange comparators for sorting loop lists by number and by area. 2010-12-17 18:13:52 +00:00
MachineModuleInfo.cpp Fixed version of 121434 with no new memory leaks. 2010-12-10 07:39:47 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Use IndexedMap for MachineRegisterInfo as well. No functional change. 2011-01-09 03:05:46 +00:00
MachineSink.cpp
MachineSSAUpdater.cpp
MachineVerifier.cpp Verify slot index ordering. 2011-01-12 21:27:48 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp
PeepholeOptimizer.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
PHIElimination.cpp Speculatively revert r123384 to make llvm-gcc-i386-linux-selfhost buildbot happy. 2011-01-13 19:27:50 +00:00
PHIEliminationUtils.cpp Move the FindCopyInsertPoint method of PHIElimination to a new standalone 2010-12-05 19:51:05 +00:00
PHIEliminationUtils.h Move the FindCopyInsertPoint method of PHIElimination to a new standalone 2010-12-05 19:51:05 +00:00
PostRASchedulerList.cpp Various bits of framework needed for precise machine-level selection 2010-12-24 05:03:26 +00:00
PreAllocSplitting.cpp Remove some checks for StrongPHIElim. These checks make it impossible to use an 2010-12-19 18:03:27 +00:00
ProcessImplicitDefs.cpp None of the other pass names in CodeGen have terminating periods. 2010-12-29 11:49:10 +00:00
PrologEpilogInserter.cpp Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp Merge System into Support. 2010-11-29 18:16:10 +00:00
README.txt
RegAllocBase.h Add a missing word to a comment. 2010-12-29 04:42:39 +00:00
RegAllocBasic.cpp Pass a Banner argument to the machine code verifier both from 2010-12-18 00:06:56 +00:00
RegAllocFast.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
RegAllocGreedy.cpp Pacify the compiler. BestWeight cannot in fact be used uninitialized 2010-12-28 10:07:15 +00:00
RegAllocLinearScan.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
RegAllocPBQP.cpp Fix some style issues in PBQP. Patch by David Blaikie. 2010-11-12 05:47:21 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp
RenderMachineFunction.cpp
RenderMachineFunction.h
ScheduleDAG.cpp Fix a few cases where the scheduler is not checking for phys reg copies. The scheduling node may have a NULL DAG node, yuck. 2010-12-24 06:46:50 +00:00
ScheduleDAGEmit.cpp Change all self assignments X=X to (void)X, so that we can turn on a 2010-12-23 00:58:24 +00:00
ScheduleDAGInstrs.cpp Do not model all INLINEASM instructions as having unmodelled side effects. 2011-01-07 23:50:32 +00:00
ScheduleDAGInstrs.h
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp Various bits of framework needed for precise machine-level selection 2010-12-24 05:03:26 +00:00
ShadowStackGC.cpp
ShrinkWrapping.cpp
SimpleRegisterCoalescing.cpp Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance. 2011-01-09 03:05:53 +00:00
SimpleRegisterCoalescing.h Implement the first half of LiveDebugVariables. 2010-12-02 00:37:37 +00:00
SjLjEHPrepare.cpp Early exit if we don't have invokes. The 'Unwinds' vector isn't modified unless 2011-01-07 02:54:45 +00:00
SlotIndexes.cpp Insert two blank SlotIndexes between basic blocks instead of just one. 2010-11-11 00:19:20 +00:00
Spiller.cpp Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual and 2011-01-09 21:17:37 +00:00
Spiller.h Force the greedy register allocator to always use the inline spiller. 2010-12-10 22:54:44 +00:00
SpillPlacement.cpp Add the SpillPlacement analysis pass. 2011-01-06 01:21:53 +00:00
SpillPlacement.h Add the SpillPlacement analysis pass. 2011-01-06 01:21:53 +00:00
SplitKit.cpp Turn the EdgeBundles class into a stand-alone machine CFG analysis pass. 2011-01-04 21:10:05 +00:00
SplitKit.h Turn the EdgeBundles class into a stand-alone machine CFG analysis pass. 2011-01-04 21:10:05 +00:00
Splitter.cpp
Splitter.h
StackProtector.cpp Make more passes preserve dominators (or state that they preserve dominators if 2011-01-08 17:01:52 +00:00
StackSlotColoring.cpp Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual and 2011-01-09 21:17:37 +00:00
StrongPHIElimination.cpp Eliminate some extra hash table lookups. 2011-01-09 10:54:21 +00:00
TailDuplication.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
TargetInstrInfoImpl.cpp Do not model all INLINEASM instructions as having unmodelled side effects. 2011-01-07 23:50:32 +00:00
TargetLoweringObjectFileImpl.cpp Fixed version of 121434 with no new memory leaks. 2010-12-10 07:39:47 +00:00
TwoAddressInstructionPass.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
UnreachableBlockElim.cpp Make more passes preserve dominators (or state that they preserve dominators if 2011-01-08 17:01:52 +00:00
VirtRegMap.cpp Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. 2011-01-10 02:58:51 +00:00
VirtRegMap.h Add a forgotten VireReg2IndexFunctor. 2011-01-09 18:58:33 +00:00
VirtRegRewriter.cpp Teach VirtRegRewriter to update slot indexes when erasing instructions. 2011-01-12 22:28:51 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.