Force the greedy register allocator to always use the inline spiller.

Soon, RegAllocGreedy will start splitting live ranges, and then deferred
spilling won't work anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121591 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-12-10 22:54:44 +00:00
parent 3bda29eb4f
commit f6dff84d4e
3 changed files with 8 additions and 7 deletions

View File

@ -311,7 +311,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
getAnalysis<LiveIntervals>());
ReservedRegs = TRI->getReservedRegs(*MF);
SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
allocatePhysRegs();
addMBBLiveIns(MF);

View File

@ -231,12 +231,6 @@ public:
} // end anonymous namespace
namespace llvm {
Spiller *createInlineSpiller(MachineFunctionPass &pass,
MachineFunction &mf,
VirtRegMap &vrm);
}
llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
MachineFunction &mf,
VirtRegMap &vrm) {

View File

@ -44,6 +44,13 @@ namespace llvm {
Spiller* createSpiller(MachineFunctionPass &pass,
MachineFunction &mf,
VirtRegMap &vrm);
/// Create and return a spiller that will insert spill code directly instead
/// of deferring though VirtRegMap.
Spiller *createInlineSpiller(MachineFunctionPass &pass,
MachineFunction &mf,
VirtRegMap &vrm);
}
#endif