llvm-6502/test/CodeGen
Reid Kleckner a8b46e7055 WinEH: Create an unwind help alloca for __CxxFrameHandler3 xdata tables
We don't have any logic to emit those tables yet, so the sdag lowering
of this intrinsic is just a stub. We can see the intrinsic in the
prepared IR, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233209 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-25 20:10:36 +00:00
..
AArch64 [AArch64, ARM] Enable GlobalMerge with -O3 rather than -O1. 2015-03-23 21:17:36 +00:00
ARM [AArch64, ARM] Enable GlobalMerge with -O3 rather than -O1. 2015-03-23 21:17:36 +00:00
BPF
CPP
Generic Unxfail test/CodeGen/Generic/vector.ll now passing on Hexagon 2015-03-19 20:22:17 +00:00
Hexagon
Inputs
Mips [mips] Support 16-bit offsets for 'm' inline assembly memory constraint. 2015-03-24 15:19:14 +00:00
MSP430
NVPTX Add support for __nvvm_reflect changes in libdevice in CUDA-7.0 2015-03-19 17:05:35 +00:00
PowerPC Add Hardware Transactional Memory (HTM) Support 2015-03-25 19:36:23 +00:00
R600 R600/SI: Select V_BFE_U32 for and+shift with a non-literal offset 2015-03-24 13:40:34 +00:00
SPARC
SystemZ
Thumb [ARM] Fix handling of thumb1 out-of-range frame offsets 2015-03-20 17:20:07 +00:00
Thumb2 Fix a nasty bug in DAGCombine of STORE nodes. 2015-03-19 22:48:57 +00:00
WinEH WinEH: Create an unwind help alloca for __CxxFrameHandler3 xdata tables 2015-03-25 20:10:36 +00:00
X86 [X86, AVX] improve insertion into zero element of 256-bit vector 2015-03-25 17:36:01 +00:00
XCore