llvm-6502/lib/Target/Sparc
Jakob Stoklund Olesen 17ca0f8f80 Implement SPARCv9 atomic_swap_64 with a pseudo.
The SWAP instruction only exists in a 32-bit variant, but the 64-bit
atomic swap can be implemented in terms of CASX, like the other atomic
rmw primitives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200453 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:48:46 +00:00
..
AsmParser Change MCStreamer EmitInstruction interface to take subtarget info 2014-01-28 23:12:42 +00:00
Disassembler [Sparc] Replace (unsigned)-1 with ~OU as suggested by Reid Kleckner. 2014-01-12 04:34:31 +00:00
InstPrinter [Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl. 2014-01-10 01:48:17 +00:00
MCTargetDesc [Sparc] Use %r_disp32 for pc_rel entries in FDE as well. 2014-01-29 06:59:20 +00:00
TargetInfo Prune redundant dependencies in LLVMBuild.txt. 2013-12-11 00:30:57 +00:00
CMakeLists.txt [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame. 2014-01-29 04:51:35 +00:00
DelaySlotFiller.cpp [Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify-machineinstrs with SPARC backend. 2014-01-11 19:38:03 +00:00
LLVMBuild.txt [Sparc] Add initial implementation of disassembler for sparc 2014-01-06 08:08:58 +00:00
Makefile [Sparc] Add initial implementation of disassembler for sparc 2014-01-06 08:08:58 +00:00
README.txt
Sparc.h [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter. 2013-12-26 01:49:59 +00:00
Sparc.td Only generate the popc instruction for SPARC CPUs that implement it. 2014-01-26 06:09:59 +00:00
SparcAsmPrinter.cpp [Sparc] Fix breakage in r200345 2014-01-28 23:38:16 +00:00
SparcCallingConv.td The SPARCv9 ABI returns a float in %f0. 2014-01-12 04:13:17 +00:00
SparcCodeEmitter.cpp [SparcV9] Add support for JIT in Sparc64. 2014-01-24 07:10:19 +00:00
SparcFrameLowering.cpp SparcFrameLowering.cpp: Prune 'DL' [-Wunused-variable] 2013-11-25 00:52:46 +00:00
SparcFrameLowering.h [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64. 2013-11-24 20:23:25 +00:00
SparcInstr64Bit.td Implement SPARCv9 atomic_swap_64 with a pseudo. 2014-01-30 04:48:46 +00:00
SparcInstrAliases.td [Sparc] Emit retl/ret instead of jmp instruction. It improves the readability of the assembly generated. 2014-01-10 02:55:27 +00:00
SparcInstrFormats.td [SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly. 2014-01-08 07:47:57 +00:00
SparcInstrInfo.cpp [SparcV9] Use correct register class (I64RegClass) to hold the address of _GLOBAL_OFFSET_TABLE_ in sparcv9. 2014-01-29 03:35:08 +00:00
SparcInstrInfo.h [weak vtables] Remove a bunch of weak vtables 2013-11-19 00:57:56 +00:00
SparcInstrInfo.td [SparcV9] Use correct register class (I64RegClass) to hold the address of _GLOBAL_OFFSET_TABLE_ in sparcv9. 2014-01-29 03:35:08 +00:00
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp Implement SPARCv9 atomic_swap_64 with a pseudo. 2014-01-30 04:48:46 +00:00
SparcISelLowering.h Implement atomicrmw operations in 32 and 64 bits for SPARCv9. 2014-01-24 06:23:31 +00:00
SparcJITInfo.cpp [SparcV9] Add support for JIT in Sparc64. 2014-01-24 07:10:19 +00:00
SparcJITInfo.h [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcMCInstLower.cpp Move the llvm mangler to lib/IR. 2014-01-07 21:19:40 +00:00
SparcRegisterInfo.cpp [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64. 2013-11-24 20:23:25 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcRelocations.h [SparcV9] Add support for JIT in Sparc64. 2014-01-24 07:10:19 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp Clean up the Legal/Expand logic for SPARC popc. 2014-01-26 08:12:34 +00:00
SparcSubtarget.h Only generate the popc instruction for SPARC CPUs that implement it. 2014-01-26 06:09:59 +00:00
SparcTargetMachine.cpp Make the llvm mangler depend only on DataLayout. 2014-01-03 19:21:54 +00:00
SparcTargetMachine.h [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
SparcTargetObjectFile.cpp [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame. 2014-01-29 04:51:35 +00:00
SparcTargetObjectFile.h [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame. 2014-01-29 04:51:35 +00:00
SparcTargetStreamer.h Construct the MCStreamer before constructing the MCTargetStreamer. 2014-01-26 06:06:37 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.