David Chisnall aa5b393c69 Expose move to/from coprocessor instructions in MIPS64 mode. ... Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165711 91177308-0d34-0410-b5e6-96231b3b80d8		2012-10-11 10:21:34 +00:00
..
ARM	Test case for r165480.	2012-10-10 02:54:23 +00:00
AsmParser	Add support for macro parameters/arguments delimited by spaces,	2012-09-19 20:36:12 +00:00
COFF	Emit dtors into proper section while compiling in vcpp-compatible mode.	2012-09-23 15:53:47 +00:00
Disassembler	Diagnose invalid alignments on duplicating VLDn instructions.	2012-09-06 15:27:12 +00:00
ELF	MC: Overhaul handling of .lcomm	2012-09-07 17:25:13 +00:00
MachO	MachO: direct-to-object attribute for data-in-code markers.	2012-10-01 22:20:54 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	Expose move to/from coprocessor instructions in MIPS64 mode.	2012-10-11 10:21:34 +00:00
X86	llvm/test/MC/X86/x86_nop.s: Make sure -arch=x86 when -mcpu=geode.	2012-09-19 00:56:20 +00:00