Toma Tabacu aafe2ca7d5 [mips] [IAS] Add partial support for the ULW pseudo-instruction. ...

Summary:
This only adds support for ULW of an immediate address with/without a source register.
It does not include support for ULW of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240782 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-26 13:20:17 +00:00

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Analysis

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Assembler

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Bindings

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Bitcode

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BugPoint

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CodeGen

[ARM] Cortex-R4F is not VFPOnlySP

2015-06-26 12:14:56 +00:00

DebugInfo

Make llvm-dwarfdump exit with non-zero exit code if error was occured.

2015-06-25 23:40:15 +00:00

ExecutionEngine

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Feature

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FileCheck

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Instrumentation

[asan] Do not instrument special purpose LLVM sections.

2015-06-25 23:35:48 +00:00

Integer

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JitListener

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LibDriver

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Linker

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LTO

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MC

[mips] [IAS] Add partial support for the ULW pseudo-instruction.

2015-06-26 13:20:17 +00:00

Object

[Object][ELF] Add support for dumping dynamic relocations when sections are stripped.

2015-06-25 21:47:32 +00:00

Other

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SymbolRewriter

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TableGen

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tools

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Transforms

[InstCombine] call SimplifyICmpInst with correct context

2015-06-25 20:14:47 +00:00

Unit

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Verifier

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YAMLParser

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.clang-format

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CMakeLists.txt

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lit.cfg

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lit.site.cfg.in

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Makefile

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Makefile.tests

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TestRunner.sh

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