Nate Begeman abc0199680 Adapt the x86 build_vector dagcombine to the current state of the legalizer. ... build vectors with i64 elements will only appear on 32b x86 before legalize. Since vector widening occurs during legalize, and produces i64 build_vector elements, the dag combiner is never run on these before legalize splits them into 32b elements. Teach the build_vector dag combine in x86 back end to recognize consecutive loads producing the low part of the vector. Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes since that was required implicitly. Add a testcase for the transform. Old: subl $28, %esp movl 32(%esp), %eax movl 4(%eax), %ecx movl %ecx, 4(%esp) movl (%eax), %eax movl %eax, (%esp) movaps (%esp), %xmm0 pmovzxwd %xmm0, %xmm0 movl 36(%esp), %eax movaps %xmm0, (%eax) addl $28, %esp ret New: movl 4(%esp), %eax pmovzxwd (%eax), %xmm0 movl 8(%esp), %eax movaps %xmm0, (%eax) ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8		2009-06-05 21:37:30 +00:00
..
Alpha
ARM	Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.	2009-06-05 19:08:58 +00:00
CBackend	Fix an erroneous check for isFNeg; the FNeg case is handled	2009-06-04 23:43:29 +00:00
CellSPU	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
CPP
Generic	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
IA64
Mips	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
MSP430	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
PowerPC	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
SPARC	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
X86	Adapt the x86 build_vector dagcombine to the current state of the legalizer.	2009-06-05 21:37:30 +00:00
XCore	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00