6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-07 14:33:15 +00:00
Code Issues Projects Releases Wiki Activity
llvm-6502/test/CodeGen/X86
History
Nate Begeman abc0199680 Adapt the x86 build_vector dagcombine to the current state of the legalizer. 
build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72957 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05 21:37:30 +00:00
..
2002-12-23-LocalRAProblem.ll
…
2002-12-23-SubProblem.ll
…
2003-08-03-CallArgLiveRanges.ll
…
2003-08-23-DeadBlockTest.ll
…
2003-11-03-GlobalBool.ll
…
2004-02-12-Memcpy.ll
…
2004-02-13-FrameReturnAddress.ll
…
2004-02-14-InefficientStackPointer.ll
…
2004-02-22-Casts.ll
…
2004-03-30-Select-Max.ll
…
2004-04-09-SameValueCoalescing.ll
…
2004-04-13-FPCMOV-Crash.ll
…
2004-06-10-StackifierCrash.ll
…
2004-10-08-SelectSetCCFold.ll
…
2005-01-17-CycleInDAG.ll
…
2005-02-14-IllegalAssembler.ll
…
2005-05-08-FPStackifierPHI.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2006-01-19-ISelFoldingBug.ll
…
2006-03-01-InstrSchedBug.ll
…
2006-03-02-InstrSchedBug.ll
…
2006-04-04-CrossBlockCrash.ll
…
2006-04-27-ISelFoldingBug.ll
…
2006-05-01-SchedCausingSpills.ll
…
2006-05-02-InstrSched1.ll
…
2006-05-02-InstrSched2.ll
…
2006-05-08-CoalesceSubRegClass.ll
…
2006-05-08-InstrSched.ll
…
2006-05-11-InstrSched.ll
Change these tests to use regular loads instead of llvm.x86.sse2.loadu.dq.
2009-02-16 00:44:23 +00:00
2006-05-17-VectorArg.ll
…
2006-05-22-FPSetEQ.ll
…
2006-05-25-CycleInDAG.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2006-07-10-InlineAsmAConstraint.ll
…
2006-07-12-InlineAsmQConstraint.ll
…
2006-07-19-ATTAsm.ll
…
2006-07-20-InlineAsm.ll
…
2006-07-28-AsmPrint-Long-As-Pointer.ll
…
2006-07-31-SingleRegClass.ll
…
2006-08-07-CycleInDAG.ll
…
2006-08-16-CycleInDAG.ll
…
2006-08-21-ExtraMovInst.ll
…
2006-09-01-CycleInDAG.ll
…
2006-10-02-BoolRetCrash.ll
…
2006-10-07-ScalarSSEMiscompile.ll
…
2006-10-09-CycleInDAG.ll
…
2006-10-10-FindModifiedNodeSlotBug.ll
…
2006-10-12-CycleInDAG.ll
…
2006-10-13-CycleInDAG.ll
…
2006-10-19-SwitchUnnecessaryBranching.ll
Add an explicit -asm-verbose to these tests, to make it
2009-03-31 18:20:47 +00:00
2006-11-12-CSRetCC.ll
…
2006-11-17-IllegalMove.ll
…
2006-11-27-SelectLegalize.ll
…
2006-11-28-Memcpy.ll
…
2006-12-19-IntelSyntax.ll
…
2007-01-08-InstrSched.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-01-13-StackPtrIndex.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-01-29-InlineAsm-ir.ll
…
2007-02-04-OrAddrMode.ll
…
2007-02-19-LiveIntervalAssert.ll
…
2007-02-25-FastCCStack.ll
…
2007-03-01-SpillerCrash.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-03-15-GEP-Idx-Sink.ll
…
2007-03-16-InlineAsm.ll
…
2007-03-18-LiveIntervalAssert.ll
…
2007-03-24-InlineAsmMultiRegConstraint.ll
…
2007-03-24-InlineAsmPModifier.ll
…
2007-03-24-InlineAsmVectorOp.ll
…
2007-03-24-InlineAsmXConstraint.ll
…
2007-03-26-CoalescerBug.ll
…
2007-04-08-InlineAsmCrash.ll
…
2007-04-11-InlineAsmVectorResult.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-04-17-LiveIntervalAssert.ll
…
2007-04-24-Huge-Stack.ll
…
2007-04-24-VectorCrash.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-04-25-MMX-PADDQ.ll
…
2007-04-27-InlineAsm-IntMemInput.ll
…
2007-05-05-VecCastExpand.ll
…
2007-05-07-InvokeSRet.ll
…
2007-05-14-LiveIntervalAssert.ll
…
2007-05-15-maskmovq.ll
…
2007-05-17-ShuffleISelBug.ll
…
2007-06-04-tailmerge4.ll
Add an explicit -asm-verbose to these tests, to make it
2009-03-31 18:20:47 +00:00
2007-06-04-X86-64-CtorAsmBugs.ll
…
2007-06-05-LSR-Dominator.ll
…
2007-06-14-branchfold.ll
…
2007-06-15-IntToMMX.ll
…
2007-06-28-X86-64-isel.ll
…
2007-06-29-DAGCombinerBug.ll
…
2007-06-29-VecFPConstantCSEBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-07-03-GR64ToVR64.ll
…
2007-07-10-StackerAssert.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-07-18-Vector-Extract.ll
…
2007-08-01-LiveVariablesBug.ll
…
2007-08-09-IllegalX86-64Asm.ll
…
2007-08-10-SignExtSubreg.ll
Revert 67132. This is breaking some objective-c apps.
2009-03-25 20:20:11 +00:00
2007-08-13-AppendingLinkage.ll
…
2007-08-13-SpillerReuse.ll
…
2007-09-03-X86-64-EhSelector.ll
…
2007-09-05-InvalidAsm.ll
…
2007-09-06-ExtWeakAliasee.ll
…
2007-09-17-ObjcFrameEH.ll
…
2007-09-18-ShuffleXformBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-09-27-LDIntrinsics.ll
…
2007-10-04-AvoidEFLAGSCopy.ll
…
2007-10-05-3AddrConvert.ll
Teach LSR sink to sink the immediate portion of the common expression back into uses if they fit in address modes of all the uses.
2009-02-21 02:06:47 +00:00
2007-10-12-CoalesceExtSubReg.ll
…
2007-10-12-SpillerUnfold1.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-10-12-SpillerUnfold2.ll
…
2007-10-14-CoalescerCrash.ll
…
2007-10-15-CoalescerCrash.ll
…
2007-10-16-CoalescerCrash.ll
…
2007-10-16-fp80_select.ll
…
2007-10-16-IllegalAsm.ll
…
2007-10-17-IllegalAsm.ll
…
2007-10-19-SpillerUnfold.ll
…
2007-10-28-inlineasm-q-modifier.ll
…
2007-10-29-ExtendSetCC.ll
…
2007-10-30-LSRCrash.ll
…
2007-10-31-extractelement-i64.ll
…
2007-11-01-ISelCrash.ll
…
2007-11-02-BadAsm.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-11-03-x86-64-q-constraint.ll
…
2007-11-04-LiveIntervalCrash.ll
…
2007-11-04-LiveVariablesBug.ll
…
2007-11-04-rip-immediate-constant.ll
…
2007-11-06-InstrSched.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-11-07-MulBy4.ll
…
2007-11-14-Coalescer-Bug.ll
…
2007-11-30-LoadFolding-Bug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-11-30-TestLoadFolding.ll
…
2007-12-11-FoldImpDefSpill.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-12-16-BURRSchedCrash.ll
…
2007-12-18-LoadCSEBug.ll
…
2008-01-08-IllegalCMP.ll
…
2008-01-08-SchedulerCrash.ll
…
2008-01-09-LongDoubleSin.ll
…
2008-01-16-FPStackifierAssert.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-01-16-InvalidDAGCombineXform.ll
…
2008-01-16-Trampoline.ll
…
2008-01-25-EmptyFunction.ll
…
2008-02-05-ISelCrash.ll
…
2008-02-06-LoadFoldingBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-02-08-LoadFoldingBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-02-14-BitMiscompile.ll
…
2008-02-18-TailMergingBug.ll
…
2008-02-20-InlineAsmClobber.ll
Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
2009-03-23 08:01:15 +00:00
2008-02-22-LocalRegAllocBug.ll
…
2008-02-22-ReMatBug.ll
Don't use special heuristics for nodes with no data predecessors
2009-02-11 21:29:39 +00:00
2008-02-25-InlineAsmBug.ll
…
2008-02-25-X86-64-CoalescerBug.ll
…
2008-02-26-AsmDirectMemOp.ll
…
2008-02-27-DeadSlotElimBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-02-27-PEICrash.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-03-06-frem-fpstack.ll
…
2008-03-07-APIntBug.ll
…
2008-03-10-RegAllocInfLoop.ll
…
2008-03-12-ThreadLocalAlias.ll
…
2008-03-13-TwoAddrPassCrash.ll
…
2008-03-14-SpillerCrash.ll
…
2008-03-18-CoalescerBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-03-19-DAGCombinerBug.ll
…
2008-03-23-DarwinAsmComments.ll
Add an explicit -asm-verbose to these tests, to make it
2009-03-31 18:20:47 +00:00
2008-03-25-TwoAddrPassBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-03-31-SpillerFoldingBug.ll
…
2008-04-02-unnamedEH.ll
…
2008-04-08-CoalescerCrash.ll
…
2008-04-09-BranchFolding.ll
…
2008-04-15-LiveVariableBug.ll
Second attempt:
2009-04-29 00:15:41 +00:00
2008-04-16-CoalescerBug.ll
…
2008-04-16-ReMatBug.ll
…
2008-04-17-CoalescerBug.ll
…
2008-04-24-MemCpyBug.ll
…
2008-04-24-pblendw-fold-crash.ll
…
2008-04-26-Asm-Optimize-Imm.ll
…
2008-04-28-CoalescerBug.ll
…
2008-04-28-CyclicSchedUnit.ll
…
2008-05-01-InvalidOrdCompare.ll
…
2008-05-09-PHIElimBug.ll
…
2008-05-09-ShuffleLoweringBug.ll
…
2008-05-12-tailmerge-5.ll
…
2008-05-21-CoalescerBug.ll
Second attempt:
2009-04-29 00:15:41 +00:00
2008-05-22-FoldUnalignedLoad.ll
…
2008-05-28-CoalescerBug.ll
…
2008-05-28-LocalRegAllocBug.ll
…
2008-06-04-MemCpyLoweringBug.ll
…
2008-06-13-NotVolatileLoadStore.ll
…
2008-06-13-VolatileLoadStore.ll
…
2008-06-16-SubregsBug.ll
…
2008-06-18-BadShuffle.ll
…
2008-06-25-VecISelBug.ll
…
2008-07-07-DanglingDeadInsts.ll
…
2008-07-09-ELFSectionAttributes.ll
…
2008-07-11-SHLBy1.ll
…
2008-07-11-SpillerBug.ll
Fix test after Chris' select changes.
2009-03-12 16:10:08 +00:00
2008-07-16-CoalescerCrash.ll
…
2008-07-19-movups-spills.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-07-22-CombinerCrash.ll
…
2008-07-23-VSetCC.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-08-05-SpillerBug.ll
Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g.
2009-04-20 08:01:12 +00:00
2008-08-06-RewriterBug.ll
…
2008-08-17-UComiCodeGenBug.ll
…
2008-08-19-SubAndFetch.ll
…
2008-08-23-64Bit-maskmovq.ll
…
2008-08-23-X86-64AsmBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-08-25-AsmRegTypeMismatch.ll
…
2008-08-31-EH_RETURN32.ll
…
2008-08-31-EH_RETURN64.ll
…
2008-09-05-sinttofp-2xi32.ll
…
2008-09-09-LinearScanBug.ll
…
2008-09-11-CoalescerBug2.ll
…
2008-09-11-CoalescerBug.ll
…
2008-09-17-inline-asm-1.ll
…
2008-09-18-inline-asm-2.ll
Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
2009-03-23 08:01:15 +00:00
2008-09-19-RegAllocBug.ll
…
2008-09-25-sseregparm-1.ll
…
2008-09-26-FrameAddrBug.ll
…
2008-09-29-ReMatBug.ll
…
2008-09-29-VolatileBug.ll
…
2008-10-02-Atomics32-2.ll
Help DejaGnu avoid pipe-jam by producing less output from certain test cases.
2009-05-16 00:34:42 +00:00
2008-10-06-MMXISelBug.ll
…
2008-10-06-x87ld-nan-1.ll
…
2008-10-06-x87ld-nan-2.ll
…
2008-10-07-SSEISelBug.ll
…
2008-10-11-CallCrash.ll
…
2008-10-13-CoalescerBug.ll
…
2008-10-16-SpillerBug.ll
Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g.
2009-04-20 08:01:12 +00:00
2008-10-16-VecUnaryOp.ll
…
2008-10-17-Asm64bitRConstraint.ll
…
2008-10-20-AsmDoubleInI32.ll
…
2008-10-24-FlippedCompare.ll
…
2008-10-27-CoalescerBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-10-27-StackRealignment.ll
…
2008-10-29-ExpandVAARG.ll
…
2008-11-03-F80VAARG.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-11-06-testb.ll
…
2008-11-13-inlineasm-3.ll
…
2008-11-29-DivideConstant16bit.ll
…
2008-11-29-DivideConstant16bitSigned.ll
…
2008-11-29-ULT-Sign.ll
…
2008-12-01-loop-iv-used-outside-loop.ll
…
2008-12-01-SpillerAssert.ll
…
2008-12-02-dagcombine-1.ll
…
2008-12-02-dagcombine-2.ll
…
2008-12-02-dagcombine-3.ll
…
2008-12-02-IllegalResultType.ll
…
2008-12-05-SpillerCrash.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2008-12-16-BadShift.ll
…
2008-12-16-dagcombine-4.ll
…
2008-12-19-EarlyClobberBug.ll
Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
2009-03-23 08:01:15 +00:00
2008-12-22-dagcombine-5.ll
…
2008-12-23-crazy-address.ll
…
2008-12-23-dagcombine-6.ll
…
2009-01-12-CoalescerBug.ll
…
2009-01-13-DoubleUpdate.ll
…
2009-01-16-SchedulerBug.ll
…
2009-01-16-UIntToFP.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2009-01-18-ConstantExprCrash.ll
…
2009-01-25-NoSSE.ll
…
2009-01-26-WrongCheck.ll
…
2009-01-27-NullStrings.ll
…
2009-01-29-LocalRegAllocBug.ll
…
2009-01-31-BigShift2.ll
…
2009-01-31-BigShift3.ll
…
2009-01-31-BigShift.ll
…
2009-02-01-LargeMask.ll
…
2009-02-03-AnalyzedTwice.ll
…
2009-02-04-sext-i64-gep.ll
if we have a large GEP offset on a 32-bit or other target, make
2009-02-05 06:55:21 +00:00
2009-02-05-CoalescerBug.ll
Fix test. It produces unexpected code if sse4.1 is on.
2009-02-06 01:49:19 +00:00
2009-02-07-CoalescerBug.ll
Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed.
2009-02-09 08:45:39 +00:00
2009-02-08-CoalescerBug.ll
Fix PR3486. Fix a bug in code that manually patch physical register live interval after its sub-register is coalesced with a virtual register.
2009-02-08 11:04:35 +00:00
2009-02-11-codegenprepare-reuse.ll
fix PR3537: if resetting bbi back to the start of a block, we need to
2009-02-12 06:56:08 +00:00
2009-02-12-DebugInfoVLA.ll
fix the X86 backend to just drop llvm.declare nodes for VLAs instead of
2009-02-12 17:33:11 +00:00
2009-02-12-InlineAsm-nieZ-constraints.ll
Arrange to print constants that match "n" and "i" constraints
2009-02-12 20:58:09 +00:00
2009-02-12-SpillerBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2009-02-20-PreAllocSplit-Crash.ll
Fix a crash in the pre-alloc splitter exposed by recent codegen changes.
2009-02-20 10:02:23 +00:00
2009-02-21-ExtWeakInitializer.ll
Drop bunch of half-working stuff in the ext_weak linkage support.
2009-02-21 11:53:32 +00:00
2009-02-25-CommuteBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2009-02-26-MachineLICMBug.ll
MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's.
2009-02-27 00:02:22 +00:00
2009-03-03-BitcastLongDouble.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2009-03-03-BTHang.ll
The DAG combiner was performing a BT combine. The BT combine had a value of -1,
2009-03-04 00:18:06 +00:00
2009-03-05-burr-list-crash.ll
Fix ScheduleDAGRRList::CopyAndMoveSuccessors' handling of nodes
2009-03-06 02:23:01 +00:00
2009-03-07-FPConstSelect.ll
reapply my previous patch (r66358) with a tweak to set the
2009-03-11 05:08:08 +00:00
2009-03-09-APIntCrash.ll
Fix PR3763 by using proper APInt methods instead of uint64_t's.
2009-03-09 20:22:18 +00:00
2009-03-09-SpillerBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2009-03-10-CoalescerBug.ll
Two coalescer fixes in one.
2009-03-11 00:03:21 +00:00
2009-03-11-CoalescerBug.ll
My last coalescer fix introduced a subtler one. It's aborting a commuting optimization too late and left the live intervals to be out of sync with instructions. This fixes 8b10b.
2009-03-11 22:18:44 +00:00
2009-03-12-CPAlignBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2009-03-13-PHIElimBug.ll
Reapply r67049, with the test adjusted for darwin
2009-03-17 09:46:22 +00:00
2009-03-16-PHIElimInLPad.ll
Add an explicit -asm-verbose to these tests, to make it
2009-03-31 18:20:47 +00:00
2009-03-16-SpillerBug.ll
THis doesn't fail.
2009-05-07 01:41:42 +00:00
2009-03-23-i80-fp80.ll
Fix internal representation of fp80 to be the
2009-03-23 21:16:53 +00:00
2009-03-23-LinearScanBug.ll
Second attempt:
2009-04-29 00:15:41 +00:00
2009-03-23-MultiUseSched.ll
For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine.
2009-06-03 21:13:54 +00:00
2009-03-25-TestBug.ll
Add -march=x86.
2009-03-26 23:03:32 +00:00
2009-03-26-NoImplicitFPBug.ll
Forgot this test.
2009-03-30 06:17:34 +00:00
2009-04-09-InlineAsmCrash.ll
reg0 references are not real registers. This fixes a crash on the
2009-04-09 16:50:43 +00:00
2009-04-12-FastIselOverflowCrash.ll
fix a cross-block fastisel crash handling overflow intrinsics.
2009-04-12 07:51:14 +00:00
2009-04-12-picrel.ll
In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching
2009-04-12 23:00:38 +00:00
2009-04-13-2AddrAssert-2.ll
Fix PR3934 part 2. findOnlyInterestingUse() was not setting IsCopy and IsDstPhys which are returned by value and used by callee. This happened to work on the earlier test cases because of a logic error in the caller side.
2009-04-14 00:32:25 +00:00
2009-04-13-2AddrAssert.ll
PR3934: Fix a bogus two-address pass assertion.
2009-04-13 20:04:24 +00:00
2009-04-14-IllegalRegs.ll
Second attempt:
2009-04-29 00:15:41 +00:00
2009-04-16-SpillerUnfold.ll
Adjust XFAIL syntax, maybe that will help. The other
2009-04-18 02:01:23 +00:00
2009-04-17-tls-fast.ll
For general dynamic TLS access we must use
2009-04-17 14:35:58 +00:00
2009-04-20-LinearScanOpt.ll
Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g.
2009-04-20 08:01:12 +00:00
2009-04-21-NoReloadImpDef.ll
It has finally happened. Spiller is now using live interval info.
2009-04-21 22:46:52 +00:00
2009-04-24.ll
Fix the syntax for a PR number in a test.
2009-04-27 15:08:34 +00:00
2009-04-25-CoalescerBug.ll
Do not share a single unknown val# for all the live ranges merged into a physical sub-register live interval. When coalescer is merging in clobbered virtaul register live interval into a physical register live interval, give each virtual register val# a separate val# in the physical register live interval. Otherwise, the coalescer would have lost track of the definitions information it needs to make correct coalescing decisions.
2009-04-25 09:25:19 +00:00
2009-04-27-CoalescerAssert.ll
Fix PR4034. Bug in LiveInterval::join when it's compacting new valno's.
2009-04-28 06:24:09 +00:00
2009-04-27-LiveIntervalsAssert2.ll
Fix for PR4051. When 2address pass delete an instruction, update kill info when necessary.
2009-04-28 02:12:36 +00:00
2009-04-27-LiveIntervalsAssert.ll
Fix PR4056. It's possible a physical register def is dead if its implicit use is deleted by two-address pass.
2009-04-27 17:36:47 +00:00
2009-04-27-LiveIntervalsBug.ll
Fix PR4076. Correctly create live interval of physical register with two-address update.
2009-04-27 20:42:46 +00:00
2009-04-29-IndirectDestOperands.ll
fix a regression handling indirect results: these need to be considered
2009-04-30 00:48:50 +00:00
2009-04-29-InlineAsmPMemoryModifier.ll
Properly print 'P' modifier on inline asm memory operands.
2009-04-28 21:49:33 +00:00
2009-04-29-LinearScanBug.ll
spillPhysRegAroundRegDefsUses() may have invalidated iterators stored in fixed_ IntervalPtrs. Reset them.
2009-04-29 07:16:34 +00:00
2009-04-29-RegAllocAssert.ll
Mark MOV8mr_NOREX and MOV8rm_NOREX as mayStore / mayLoad respectively.
2009-04-30 00:58:57 +00:00
2009-04-scale.ll
fix PR3995. A scale must be 1, 2, 4 or 8.
2009-04-16 12:34:53 +00:00
2009-05-08-InlineAsmIOffset.ll
Fix PR4152: asm constraint validation happens before dag combine, so we
2009-05-08 18:23:14 +00:00
2009-05-11-tailmerge-crash.ll
Fix PR4188. TailMerging can't tolerate inexact
2009-05-11 21:54:13 +00:00
2009-05-19-SingleElementExtractElement.ll
Add a testcase which got fixed by recent legalization work.
2009-05-28 05:10:20 +00:00
2009-05-23-available_externally.ll
available_externall linkage is not local, this was confusing the codegenerator,
2009-05-23 14:06:57 +00:00
2009-05-23-dagcombine-shifts.ll
Fix PR4254.
2009-05-23 17:29:48 +00:00
2009-05-28-DAGCombineCrash.ll
Do not try to create a MVT type of width 0.
2009-05-28 23:52:18 +00:00
2009-05-30-ISelBug.ll
(i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear the top 8 bits.
2009-05-30 08:43:27 +00:00
2009-06-02-RewriterBug.ll
Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well.
2009-06-03 09:00:27 +00:00
2009-06-03-Win64DisableRedZone.ll
PR3739, part 1: Disable the red zone on Win64.
2009-06-04 02:02:01 +00:00
2009-06-03-Win64SpillXMM.ll
PR3739, part 2: Use an explicit store to spill XMM registers. (Previously,
2009-06-04 02:32:04 +00:00
2009-06-04-VirtualLiveIn.ll
RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets.
2009-06-04 20:53:36 +00:00
20081212.ll
…
20090313-signext.ll
Revert 67132. This is breaking some objective-c apps.
2009-03-25 20:20:11 +00:00
abi-isel.ll
For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine.
2009-06-03 21:13:54 +00:00
add-trick32.ll
…
add-trick64.ll
…
add-with-overflow.ll
Second attempt:
2009-04-29 00:15:41 +00:00
aliases.ll
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
2009-03-25 01:47:28 +00:00
aligned-comm.ll
…
all-ones-vector.ll
…
alloca-align-rounding.ll
this is apparently passing now. Evan/Dan, please check
2009-03-17 20:23:43 +00:00
and-or-fold.ll
…
and-su.ll
Fix a TargetLowering optimization so that it doesn't duplicate
2009-04-03 20:11:30 +00:00
anyext-uses.ll
Generalize ExtendUsesToFormExtLoad to be usable for ANY_EXTEND,
2009-04-09 03:51:29 +00:00
arg-cast.ll
…
asm-block-labels.ll
…
asm-global-imm.ll
…
asm-indirect-mem.ll
…
atomic_op.ll
…
Atomics-32.ll
Help DejaGnu avoid pipe-jam by producing less output from certain test cases.
2009-05-16 00:34:42 +00:00
Atomics-64.ll
Help DejaGnu avoid pipe-jam by producing less output from certain test cases.
2009-05-16 00:34:42 +00:00
avoid-loop-align-2.ll
If header of inner loop is aligned, do not align the outer loop header. We don't want to add nops in the outer loop for the sake of aligning the inner loop.
2009-05-12 23:58:14 +00:00
avoid-loop-align.ll
…
bitcast2.ll
…
bitcast-int-to-vector.ll
…
bitcast.ll
…
break-anti-dependencies.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
bswap-inline-asm.ll
Recognize bswapl as bswap too.
2009-03-17 02:45:40 +00:00
bswap.ll
…
bt.ll
…
byval2.ll
…
byval3.ll
…
byval4.ll
…
byval5.ll
…
byval6.ll
…
byval7.ll
Implement support for using modeling implicit-zero-extension on x86-64
2009-04-08 00:15:30 +00:00
byval.ll
…
call-imm.ll
Fix test on non-darwin hosts.
2009-05-20 05:45:36 +00:00
call-push.ll
…
change-compare-stride-0.ll
Permit ChangeCompareStride to rewrite a comparison when the factor
2009-04-27 20:35:32 +00:00
change-compare-stride-1.ll
Permit ChangeCompareStride to rewrite a comparison when the factor
2009-04-27 20:35:32 +00:00
clz.ll
…
cmp0.ll
…
cmp1.ll
…
cmp2.ll
…
cmp-test.ll
…
coalescer-commute1.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
coalescer-commute2.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
coalescer-commute3.ll
…
coalescer-commute4.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
coalescer-commute5.ll
…
coalescer-remat.ll
…
code_placement.ll
Enable loop bb placement optimization.
2009-05-08 23:35:49 +00:00
codegen-prepare-cast.ll
Fix CodeGenPrepare's address-mode sinking to handle unusual
2009-06-02 21:29:13 +00:00
combine-lds.ll
…
commute-cmov.ll
…
commute-intrinsic.ll
…
commute-two-addr.ll
…
compare_folding.ll
…
compare-add.ll
…
complex-fca.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
const-select.ll
Revert 67132. This is breaking some objective-c apps.
2009-03-25 20:20:11 +00:00
constant-pool-remat-0.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
convert-2-addr-3-addr-inc64.ll
rename test to avoid messing with tab completion of dates.
2009-02-12 06:54:55 +00:00
copysign-zero.ll
…
critical-edge-split.ll
Explicitly pass -tailcallopt=false to these tests so that they
2009-04-23 19:39:41 +00:00
cstring.ll
GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well.
2009-02-18 02:19:52 +00:00
dag-rauw-cse.ll
…
dagcombine-buildvector.ll
Adapt the x86 build_vector dagcombine to the current state of the legalizer.
2009-06-05 21:37:30 +00:00
dagcombine-cse.ll
…
darwin-bzero.ll
…
darwin-no-dead-strip.ll
…
darwin-stub.ll
…
dg.exp
…
div_const.ll
…
divrem.ll
…
dollar-name.ll
…
dyn-stackalloc.ll
Fully escape the grep string for this test.
2009-04-08 00:54:40 +00:00
epilogue.ll
…
extend.ll
…
extern_weak.ll
…
extmul64.ll
…
extmul128.ll
…
extract-combine.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
extractelement-from-arg.ll
…
extractelement-load.ll
…
extractelement-shuffle.ll
…
extractps.ll
…
fabs.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fast-cc-callee-pops.ll
…
fast-cc-merge-stack-adj.ll
…
fast-cc-pass-in-regs.ll
…
fast-isel-bail.ll
Second attempt:
2009-04-29 00:15:41 +00:00
fast-isel-call.ll
…
fast-isel-gep-sext.ll
Second attempt:
2009-04-29 00:15:41 +00:00
fast-isel-i1.ll
Fix FastISel's assumption that i1 values are always zero-extended
2009-03-13 20:42:20 +00:00
fast-isel-mem.ll
…
fast-isel-phys.ll
Improve FastISel's handling of truncates to i1, and implement
2009-03-13 23:53:06 +00:00
fast-isel-shift-imm.ll
Second attempt:
2009-04-29 00:15:41 +00:00
fast-isel-tailcall.ll
X86FastISel doesn't support the -tailcallopt ABI.
2009-05-04 19:50:33 +00:00
fast-isel-tls.ll
Fast-isel can't do TLS yet, so it should fall back to SDISel
2009-02-23 22:03:08 +00:00
fast-isel-trunc.ll
Improve FastISel's handling of truncates to i1, and implement
2009-03-13 23:53:06 +00:00
fast-isel.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fastcall-correct-mangling.ll
…
fastcc-2.ll
…
fastcc-byval.ll
Explicitly pass -tailcallopt=false to these tests so that they
2009-04-23 19:39:41 +00:00
fastcc-sret.ll
Explicitly pass -tailcallopt=false to these tests so that they
2009-04-23 19:39:41 +00:00
fastcc.ll
…
field-extract-use-trunc.ll
…
fildll.ll
…
fmul-zero.ll
Check in test changes that I accidentally left out of r72872.
2009-06-04 18:22:31 +00:00
fold-add.ll
Enhance address-mode folding of ISD::ADD to handle cases where the
2009-03-13 02:25:09 +00:00
fold-and-shift.ll
…
fold-call-2.ll
…
fold-call-3.ll
…
fold-call.ll
…
fold-imm.ll
…
fold-load.ll
…
fold-mul-lohi.ll
Add nounwind to this test.
2009-05-13 22:29:12 +00:00
fold-pcmpeqd-0.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fold-pcmpeqd-1.ll
…
fold-pcmpeqd-2.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fold-sext-trunc.ll
When transforming sext(trunc(load(x))) into sext(smaller load(x)),
2009-04-27 02:00:55 +00:00
fp2sint.ll
…
fp_constant_op.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fp_load_cast_fold.ll
…
fp_load_fold.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fp-immediate-shorten.ll
…
fp-in-intregs.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fp-stack-2results.ll
…
fp-stack-compare.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fp-stack-direct-ret.ll
…
fp-stack-ret-conv.ll
…
fp-stack-ret-store.ll
…
fp-stack-ret.ll
…
fp-stack-retcopy.ll
…
fp-stack-set-st1.ll
Implement FpSET_ST1_*.
2009-02-09 23:32:07 +00:00
fsxor-alignment.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
full-lsr.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
ga-offset.ll
For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine.
2009-06-03 21:13:54 +00:00
h-register-addressing-32.ll
Implement x86 h-register extract support.
2009-04-13 16:09:41 +00:00
h-register-addressing-64.ll
Implement x86 h-register extract support.
2009-04-13 16:09:41 +00:00
h-register-store.ll
Implement x86 h-register extract support.
2009-04-13 16:09:41 +00:00
h-registers-0.ll
When the result of an EXTRACT_SUBREG, INSERT_SUBREG, or SUBREG_TO_REG
2009-04-14 22:17:14 +00:00
h-registers-1.ll
When the result of an EXTRACT_SUBREG, INSERT_SUBREG, or SUBREG_TO_REG
2009-04-14 22:17:14 +00:00
h-registers-2.ll
Fix the RUN lines so that this test actually tests.
2009-04-14 22:50:17 +00:00
h-registers-3.ll
More h-registers tricks: folding zext nodes.
2009-05-29 01:44:43 +00:00
hidden-vis-2.ll
…
hidden-vis-3.ll
…
hidden-vis-4.ll
…
hidden-vis.ll
…
i2k.ll
…
i64-mem-copy.ll
Typo.
2009-03-12 17:07:39 +00:00
i128-and-beyond.ll
…
i128-immediate.ll
…
i128-mul.ll
…
i128-ret.ll
…
i256-add.ll
…
iabs.ll
…
illegal-asm.ll
Update test for pr3864.
2009-03-23 18:27:36 +00:00
illegal-insert.ll
…
illegal-vector-args-return.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
imp-def-copies.ll
…
imul-lea-2.ll
Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
2009-03-28 05:57:29 +00:00
imul-lea.ll
…
inline-asm-2addr.ll
Turn a 2-address instruction into a 3-address one when it's profitable even if the two-address operand is killed.
2009-03-30 21:34:07 +00:00
inline-asm-flag-clobber.ll
Rename test.
2009-03-04 02:47:25 +00:00
inline-asm-fpstack.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
inline-asm-mrv.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
inline-asm-out-regs.ll
Implement x86 h-register extract support.
2009-04-13 16:09:41 +00:00
inline-asm-pic.ll
…
inline-asm-x-scalar.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
inline-asm.ll
…
ins_subreg_coalesce-1.ll
…
ins_subreg_coalesce-2.ll
…
ins_subreg_coalesce-3.ll
…
insertelement-copytoregs.ll
…
insertelement-legalize.ll
…
invalid-shift-immediate.ll
…
isel-sink2.ll
Don't force promotion of return arguments on the callee.
2009-03-17 23:43:59 +00:00
isel-sink3.ll
…
isel-sink.ll
…
isint.ll
…
isnan2.ll
…
isnan.ll
…
ispositive.ll
…
iv-users-in-other-loops.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
jump_sign.ll
…
ldzero.ll
…
lea-2.ll
…
lea-3.ll
…
lea-4.ll
…
lea-neg.ll
Make this grep line a little more specific so that it doesn't
2009-05-11 18:49:56 +00:00
lea-recursion.ll
…
lea.ll
…
legalizedag_vec.ll
Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.
2009-02-25 22:49:59 +00:00
lfence.ll
…
limited-prec.ll
…
live-out-reg-info.ll
Fix live-out reg logic to not insert over-aggressive AssertZExt
2009-03-31 01:38:29 +00:00
local-liveness.ll
…
long-setcc.ll
…
longlong-deadload.ll
…
loop-hoist.ll
Add nounwind to a few tests.
2009-05-18 15:16:49 +00:00
loop-strength-reduce2.ll
…
loop-strength-reduce3.ll
…
loop-strength-reduce4.ll
…
loop-strength-reduce5.ll
…
loop-strength-reduce6.ll
…
loop-strength-reduce7.ll
Fix strange logic in CollectIVUsers used to determine whether all uses are
2009-02-20 22:16:49 +00:00
loop-strength-reduce8.ll
Teach LSR sink to sink the immediate portion of the common expression back into uses if they fit in address modes of all the uses.
2009-02-21 02:06:47 +00:00
loop-strength-reduce-2.ll
Teach LSR sink to sink the immediate portion of the common expression back into uses if they fit in address modes of all the uses.
2009-02-21 02:06:47 +00:00
loop-strength-reduce-3.ll
…
loop-strength-reduce.ll
…
lsr-loop-exit-cond.ll
Teach LSR to optimize more loop exit compares, i.e. change them to use postinc iv value. Previously LSR would only optimize those which are in the loop latch block. However, if LSR can prove it is safe (and profitable), it's now possible to change those not in the latch blocks to use postinc values.
2009-05-11 22:33:01 +00:00
lsr-negative-stride.ll
Teach LSR to optimize more loop exit compares, i.e. change them to use postinc iv value. Previously LSR would only optimize those which are in the loop latch block. However, if LSR can prove it is safe (and profitable), it's now possible to change those not in the latch blocks to use postinc values.
2009-05-11 22:33:01 +00:00
lsr-sort.ll
Fix LSR's IV sorting function to explicitly sort by bitwidth
2009-02-13 00:26:43 +00:00
masked-iv-safe.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
masked-iv-unsafe.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
maskmovdqu.ll
Handle llvm.x86.sse2.maskmov.dqu in 64-bit.
2009-02-10 22:06:28 +00:00
memcpy-2.ll
…
memcpy.ll
…
memmove-0.ll
…
memmove-1.ll
…
memmove-2.ll
…
memmove-3.ll
…
memmove-4.ll
…
memset64-on-x86-32.ll
…
memset-2.ll
…
memset.ll
…
mfence.ll
…
mingw-alloca.ll
…
mmx-arg-passing2.ll
…
mmx-arg-passing.ll
…
mmx-arith.ll
…
mmx-bitcast-to-i64.ll
…
mmx-copy-gprs.ll
On x86, if the only use of a i64 load is a i64 store, generate a pair of double load and store instead.
2009-03-12 05:59:15 +00:00
mmx-emms.ll
…
mmx-insert-element.ll
…
mmx-pinsrw.ll
…
mmx-punpckhdq.ll
…
mmx-s2v.ll
…
mmx-shift.ll
…
mmx-shuffle.ll
…
mmx-vzmovl-2.ll
Previously, RecursivelyDeleteDeadInstructions provided an option
2009-05-02 18:29:22 +00:00
mmx-vzmovl.ll
…
movfs.ll
Add basic support for code generation of
2009-05-05 18:52:19 +00:00
movgs.ll
…
mul64.ll
…
mul128.ll
…
mul-legalize.ll
Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"
2009-03-12 06:52:53 +00:00
mul-remat.ll
…
mul-shift-reassoc.ll
…
multiple-return-values-cross-block.ll
…
multiple-return-values.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
nancvt.ll
…
narrow_op-1.ll
Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
2009-05-28 00:35:15 +00:00
narrow_op-2.ll
Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
2009-05-28 00:35:15 +00:00
neg_fp.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
negate-add-zero.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
negative_zero.ll
…
negative-sin.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
negative-subscript.ll
Make sure constant subscript is truncated to ptr size if it may not fit.
2009-02-09 20:54:38 +00:00
nobt.ll
Make a transformation added in 63266 a bit less aggressive.
2009-02-11 19:19:41 +00:00
nofence.ll
…
nosse-error1.ll
…
nosse-error2.ll
…
nosse-varargs.ll
…
omit-label.ll
If a MachineBasicBlock has multiple ways of reaching another block,
2009-05-05 21:10:19 +00:00
opt-ext-uses.ll
…
optimize-smax.ll
…
or-branch.ll
…
overlap-shift.ll
…
packed_struct.ll
…
peep-test-0.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
peep-test-1.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
peep-test-2.ll
Arithmetic instructions don't set EFLAGS bits OF and CF bits
2009-03-07 01:58:32 +00:00
peep-vector-extract-concat.ll
…
peep-vector-extract-insert.ll
…
phys_subreg_coalesce-2.ll
…
phys_subreg_coalesce.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pic_jumptable.ll
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
2009-03-25 01:47:28 +00:00
pic-1.ll
…
pic-2.ll
…
pic-3.ll
…
pic-4.ll
…
pic-5.ll
…
pic-6.ll
…
pic-cpool.ll
reapply my previous patch (r66358) with a tweak to set the
2009-03-11 05:08:08 +00:00
pic-jtbl.ll
…
pic-load-remat.ll
…
pmul.ll
Don't use special heuristics for nodes with no data predecessors
2009-02-11 21:29:39 +00:00
postalloc-coalescing.ll
…
pr1462.ll
…
pr1489.ll
Second attempt:
2009-04-29 00:15:41 +00:00
pr1505.ll
…
pr1505b.ll
…
pr2177.ll
…
pr2182.ll
…
pr2326.ll
…
pr2623.ll
…
pr2656.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pr2659.ll
…
pr2849.ll
…
pr2924.ll
…
pr2982.ll
…
pr3154.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pr3216.ll
…
pr3241.ll
…
pr3243.ll
…
pr3244.ll
…
pr3250.ll
…
pr3317.ll
…
pr3366.ll
…
pr3457.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pr3495-2.ll
Remove a bogus assertion. It's possible a live-in available value is used by a previous instruction.
2009-02-11 23:41:57 +00:00
pr3495.ll
Reverse a loop that is counting up to a maximum to
2009-05-11 17:15:42 +00:00
pr3522.ll
Fix PR3522. It's not safe to sink into landing pad BB's.
2009-02-15 08:36:12 +00:00
pre-split1.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pre-split2.ll
Turn on machine LICM in non-fast mode.
2009-02-05 08:46:33 +00:00
pre-split3.ll
…
pre-split4.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pre-split5.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pre-split6.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pre-split7.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pre-split8.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pre-split9.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
pre-split10.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
prefetch.ll
…
private-2.ll
Quotes should be printed before private prefix; some code clean up.
2009-05-05 22:50:29 +00:00
private.ll
…
rdtsc.ll
…
red-zone2.ll
Add new function attribute - noredzone.
2009-06-04 22:05:33 +00:00
red-zone.ll
…
regpressure.ll
…
rem-2.ll
…
rem.ll
…
remat-constant.ll
For Darwin / x86_64, override -relocation-model=static to pic if the output is assembly since Darwin assembler does not really support -static codeine.
2009-06-03 21:13:54 +00:00
remat-mov-1.ll
Teach LSR to optimize more loop exit compares, i.e. change them to use postinc iv value. Previously LSR would only optimize those which are in the loop latch block. However, if LSR can prove it is safe (and profitable), it's now possible to change those not in the latch blocks to use postinc values.
2009-05-11 22:33:01 +00:00
ret-addr.ll
…
ret-i64-0.ll
…
ret-mmx.ll
Make sure this test passes on linux-ppc.
2009-02-27 00:51:50 +00:00
rip-rel-address.ll
Use %rip-relative addressing on x86-64 whenever practical, as
2009-03-14 02:33:41 +00:00
rodata-relocs.ll
Tweak test for recent relro stuff
2009-03-30 15:28:40 +00:00
rot16.ll
…
rot32.ll
…
rot64.ll
…
rotate2.ll
…
rotate.ll
…
scalar_sse_minmax.ll
…
scalar-extract.ll
…
scalar-min-max-fill-operand.ll
…
scalarize-bitcast.ll
When scalarizing a vector BITCAST, check whether the operand has vector
2009-05-11 18:30:42 +00:00
select-no-cmov.ll
generalize the previous code to use the full generality of LEA
2009-03-13 05:53:31 +00:00
select-zero-one.ll
…
select.ll
…
setoeq.ll
…
setuge.ll
…
sext-load.ll
…
sext-ret-val.ll
Add a test case for PR3779: when to promote the function return value.
2009-03-25 20:30:19 +00:00
sext-select.ll
…
sext-trunc.ll
Revert 67132. This is breaking some objective-c apps.
2009-03-25 20:20:11 +00:00
sfence.ll
…
shift-and.ll
…
shift-coalesce.ll
…
shift-codegen.ll
…
shift-combine.ll
…
shift-double.ll
…
shift-folding.ll
…
shift-i128.ll
Fully general expansion of integer shift of any size.
2009-03-31 19:39:24 +00:00
shift-i256.ll
Fully general expansion of integer shift of any size.
2009-03-31 19:39:24 +00:00
shift-one.ll
…
shl_elim.ll
…
shrink-fp-const1.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
shrink-fp-const2.ll
…
sincos.ll
…
small-byval-memcpy.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
smul-with-overflow-2.ll
…
smul-with-overflow-3.ll
…
smul-with-overflow.ll
…
soft-fp.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
split-eh-lpad-edges.ll
Revert 67132. This is breaking some objective-c apps.
2009-03-25 20:20:11 +00:00
split-select.ll
…
split-vector-rem.ll
…
sret.ll
…
sse41-extractps-bitcast-0.ll
…
sse41-extractps-bitcast-1.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
sse41-pmovx.ll
…
sse_reload_fold.ll
Don't use special heuristics for nodes with no data predecessors
2009-02-11 21:29:39 +00:00
sse-align-0.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
sse-align-1.ll
…
sse-align-2.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
sse-align-3.ll
…
sse-align-4.ll
…
sse-align-5.ll
…
sse-align-6.ll
…
sse-align-7.ll
…
sse-align-8.ll
…
sse-align-9.ll
…
sse-align-10.ll
…
sse-align-11.ll
…
sse-align-12.ll
…
sse-fcopysign.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
sse-load-ret.ll
…
sse-varargs.ll
…
stack-align.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
stack-color-with-reg-2.ll
Fixed a stack slot coloring with reg bug: do not update implicit use / def when doing forward / backward propagation.
2009-05-12 18:31:57 +00:00
stack-color-with-reg.ll
Fixed a stack slot coloring with reg bug: do not update implicit use / def when doing forward / backward propagation.
2009-05-12 18:31:57 +00:00
store_op_load_fold2.ll
…
store_op_load_fold.ll
…
store-fp-constant.ll
…
store-global-address.ll
…
storetrunc-fp.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
stride-nine-with-base-reg.ll
Expand GEPs in ScalarEvolution expressions. SCEV expressions can now
2009-04-16 03:18:22 +00:00
stride-reuse.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
sub-with-overflow.ll
…
subclass-coalesce.ll
…
subreg-to-reg-0.ll
…
subreg-to-reg-1.ll
Fix PR3934 part 2. findOnlyInterestingUse() was not setting IsCopy and IsDstPhys which are returned by value and used by callee. This happened to work on the earlier test cases because of a logic error in the caller side.
2009-04-14 00:32:25 +00:00
subreg-to-reg-2.ll
Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86
2009-03-23 07:19:58 +00:00
subreg-to-reg-3.ll
Implement support for using modeling implicit-zero-extension on x86-64
2009-04-08 00:15:30 +00:00
subreg-to-reg-4.ll
Implement support for using modeling implicit-zero-extension on x86-64
2009-04-08 00:15:30 +00:00
subreg-to-reg-5.ll
Factor the code for collecting IV users out of LSR into an IVUsers class,
2009-05-12 02:17:14 +00:00
subreg-to-reg-6.ll
Implement support for using modeling implicit-zero-extension on x86-64
2009-04-08 00:15:30 +00:00
switch-zextload.ll
Generalize ExtendUsesToFormExtLoad to be usable for ANY_EXTEND,
2009-04-09 03:51:29 +00:00
swizzle.ll
…
tailcall1.ll
…
tailcall-i1.ll
Enable tail call optimization for functions that return a struct (bug 3664) and for functions that return types that need extending (e.g i1).
2009-03-28 08:33:27 +00:00
tailcall-stackalign.ll
…
tailcall-structret.ll
Enable tail call optimization for functions that return a struct (bug 3664) and for functions that return types that need extending (e.g i1).
2009-03-28 08:33:27 +00:00
tailcall-void.ll
Make check in CheckTailCallReturnConstraints for ignorable instructions between
2009-03-28 12:36:29 +00:00
tailcallbyval64.ll
…
tailcallbyval.ll
…
tailcallfp2.ll
…
tailcallfp.ll
…
tailcallpic1.ll
…
tailcallpic2.ll
…
tailcallstack64.ll
…
test-nofold.ll
…
testl-commute.ll
…
tls1-pic.ll
Add tests for the parts of X86-64 TLS that are already implemented.
2009-04-12 10:43:41 +00:00
tls1.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls2-pic.ll
Add tests for the parts of X86-64 TLS that are already implemented.
2009-04-12 10:43:41 +00:00
tls2.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls3-pic.ll
Add tests for the parts of X86-64 TLS that are already implemented.
2009-04-12 10:43:41 +00:00
tls3.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls4-pic.ll
Add tests for the parts of X86-64 TLS that are already implemented.
2009-04-12 10:43:41 +00:00
tls4.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls5.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls6.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls7.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls8.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls9.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls10.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls11.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls12.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls13.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls14.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
tls15.ll
X86-64 TLS support for local exec and initial exec.
2009-04-13 13:02:49 +00:00
trap.ll
…
trunc-to-bool.ll
…
twoaddr-coalesce-2.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
twoaddr-coalesce.ll
Implement support for using modeling implicit-zero-extension on x86-64
2009-04-08 00:15:30 +00:00
twoaddr-delete.ll
If two-address def is dead and the instruction does not define other registers, and it doesn't produce side effects, just delete the instruction.
2009-02-21 03:14:25 +00:00
twoaddr-pass-sink.ll
…
twoaddr-remat.ll
…
uint_to_fp-2.ll
…
uint_to_fp.ll
…
umul-with-carry.ll
…
urem-i8-constant.ll
…
v4f32-immediate.ll
…
variable-sized-darwin-bzero.ll
…
variadic-node-pic.ll
…
vec_add.ll
…
vec_align.ll
…
vec_call.ll
…
vec_clear.ll
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
2009-04-27 18:41:29 +00:00
vec_ctbits.ll
…
vec_extract-sse4.ll
…
vec_extract.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_fneg.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_i64.ll
Added a x86 dag combine to increase the chances to use a
2009-04-03 02:43:30 +00:00
vec_ins_extract-1.ll
make these tests pass when run on a G5.
2009-02-20 07:10:11 +00:00
vec_ins_extract.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_insert_4.ll
…
vec_insert-2.ll
…
vec_insert-3.ll
…
vec_insert-5.ll
…
vec_insert-6.ll
…
vec_insert-7.ll
…
vec_insert-8.ll
…
vec_insert.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_loadhl.ll
…
vec_logical.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_return.ll
…
vec_select.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_set-2.ll
…
vec_set-3.ll
…
vec_set-4.ll
…
vec_set-5.ll
…
vec_set-6.ll
…
vec_set-7.ll
…
vec_set-8.ll
…
vec_set-9.ll
…
vec_set-A.ll
…
vec_set-B.ll
…
vec_set-C.ll
…
vec_set-D.ll
…
vec_set-E.ll
…
vec_set-F.ll
…
vec_set-G.ll
…
vec_set-H.ll
…
vec_set-I.ll
…
vec_set-J.ll
…
vec_set.ll
…
vec_shift2.ll
…
vec_shift3.ll
…
vec_shift.ll
…
vec_shuffle-2.ll
Generate better code for v8i16 shuffles on SSE2
2009-02-23 08:49:38 +00:00
vec_shuffle-3.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_shuffle-4.ll
…
vec_shuffle-5.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_shuffle-6.ll
…
vec_shuffle-7.ll
…
vec_shuffle-8.ll
…
vec_shuffle-9.ll
…
vec_shuffle-10.ll
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
2009-04-27 18:41:29 +00:00
vec_shuffle-11.ll
…
vec_shuffle-12.ll
Generate better code for v8i16 shuffles on SSE2
2009-02-23 08:49:38 +00:00
vec_shuffle-13.ll
Generate better code for v8i16 shuffles on SSE2
2009-02-23 08:49:38 +00:00
vec_shuffle-14.ll
…
vec_shuffle-15.ll
…
vec_shuffle-16.ll
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
2009-04-27 18:41:29 +00:00
vec_shuffle-17.ll
…
vec_shuffle-18.ll
…
vec_shuffle-19.ll
…
vec_shuffle-20.ll
…
vec_shuffle-21.ll
Generate better code for v8i16 shuffles on SSE2
2009-02-23 08:49:38 +00:00
vec_shuffle-22.ll
Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
2009-04-29 22:47:44 +00:00
vec_shuffle-23.ll
…
vec_shuffle-24.ll
…
vec_shuffle-25.ll
…
vec_shuffle-26.ll
…
vec_shuffle-27.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_shuffle-28.ll
Generate better code for v8i16 shuffles on SSE2
2009-02-23 08:49:38 +00:00
vec_shuffle-29.ll
Generate better code for v8i16 shuffles on SSE2
2009-02-23 08:49:38 +00:00
vec_shuffle-30.ll
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
2009-04-27 18:41:29 +00:00
vec_shuffle-31.ll
2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.
2009-04-27 18:41:29 +00:00
vec_shuffle-32.ll
Generate better code for v8i16 shuffles on SSE2
2009-02-23 08:49:38 +00:00
vec_shuffle-33.ll
Generate better code for v8i16 shuffles on SSE2
2009-02-23 08:49:38 +00:00
vec_shuffle-34.ll
Generate better code for v8i16 shuffles on SSE2
2009-02-23 08:49:38 +00:00
vec_shuffle-35.ll
Use the -stack-alignment option instead of using a target triple
2009-02-23 16:34:46 +00:00
vec_shuffle-36.ll
Fixed a v8i16 shuffle case that should generate a pshufb instead of a pshuflw/hw.
2009-03-11 06:35:11 +00:00
vec_shuffle-37.ll
For yonah, fix a vector shuffle case for v16i8 where we didn't properly clear some bits.
2009-03-11 18:47:57 +00:00
vec_shuffle.ll
Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
2009-04-29 22:47:44 +00:00
vec_splat-2.ll
…
vec_splat-3.ll
…
vec_splat-4.ll
…
vec_splat.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_ss_load_fold.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vec_zero_cse.ll
…
vec_zero-2.ll
…
vec_zero.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vector-intrinsics.ll
…
vector-rem.ll
…
vector-variable-idx.ll
…
vector.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
vfcmp.ll
…
volatile.ll
Second attempt:
2009-04-29 00:15:41 +00:00
vortex-bug.ll
…
vshift_scalar.ll
…
vshift_split2.ll
make these tests pass when run on a G5.
2009-02-20 07:10:11 +00:00
vshift_split.ll
…
vshift-1.ll
…
vshift-2.ll
…
vshift-3.ll
…
vshift-4.ll
…
weak.ll
…
widen_arith-1.ll
…
widen_arith-2.ll
…
widen_arith-3.ll
…
widen_arith-4.ll
…
widen_arith-5.ll
…
widen_arith-6.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
widen_cast-1.ll
…
widen_cast-2.ll
…
widen_cast-3.ll
…
widen_cast-4.ll
Fix test to account for legalization changes; I think this ends up
2009-05-23 13:15:11 +00:00
widen_cast-5.ll
…
widen_cast-6.ll
…
widen_conv-1.ll
…
widen_conv-2.ll
…
widen_conv-3.ll
…
widen_conv-4.ll
…
widen_select-1.ll
…
widen_shuffle-1.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
widen_shuffle-2.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
x86-64-and-mask.ll
…
x86-64-arg.ll
…
x86-64-asm.ll
…
x86-64-dead-stack-adjust.ll
…
x86-64-disp.ll
…
x86-64-frameaddr.ll
…
x86-64-gv-offset.ll
…
x86-64-malloc.ll
Fix codegen to compute the size of an allocation by multiplying the
2009-03-17 19:36:00 +00:00
x86-64-mem.ll
…
x86-64-pic-1.ll
…
x86-64-pic-2.ll
…
x86-64-pic-3.ll
…
x86-64-pic-4.ll
…
x86-64-pic-5.ll
…
x86-64-pic-6.ll
…
x86-64-pic-7.ll
…
x86-64-pic-8.ll
…
x86-64-pic-9.ll
…
x86-64-pic-10.ll
…
x86-64-pic-11.ll
…
x86-64-ret0.ll
…
x86-64-shortint.ll
…
x86-64-sret-return.ll
…
x86-64-varargs.ll
…
x86-frameaddr2.ll
…
x86-frameaddr.ll
…
x86-store-gv-addr.ll
Revert r72734. The Darwin assembler doesn't support the static
2009-06-03 00:37:20 +00:00
xmm-r64.ll
…
xor_not.ll
…
xor-undef.ll
…
xorl.ll
…
zero-remat.ll
…
zext-inreg-0.ll
…
zext-inreg-1.ll
…