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19a99df130
The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194755 91177308-0d34-0410-b5e6-96231b3b80d8
101 lines
2.8 KiB
C++
101 lines
2.8 KiB
C++
//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief R600 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "R600RegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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using namespace llvm;
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R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm)
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: AMDGPURegisterInfo(tm),
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TM(tm)
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{ RCW.RegWeight = 0; RCW.WeightLimit = 0;}
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BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo());
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Reserved.set(AMDGPU::ZERO);
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Reserved.set(AMDGPU::HALF);
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Reserved.set(AMDGPU::ONE);
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Reserved.set(AMDGPU::ONE_INT);
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Reserved.set(AMDGPU::NEG_HALF);
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Reserved.set(AMDGPU::NEG_ONE);
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Reserved.set(AMDGPU::PV_X);
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Reserved.set(AMDGPU::ALU_LITERAL_X);
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Reserved.set(AMDGPU::ALU_CONST);
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Reserved.set(AMDGPU::PREDICATE_BIT);
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Reserved.set(AMDGPU::PRED_SEL_OFF);
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Reserved.set(AMDGPU::PRED_SEL_ZERO);
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Reserved.set(AMDGPU::PRED_SEL_ONE);
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Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
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for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
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E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
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Reserved.set(*I);
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}
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TII->reserveIndirectRegisters(Reserved, MF);
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return Reserved;
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}
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const TargetRegisterClass *
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R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
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switch (rc->getID()) {
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case AMDGPU::GPRF32RegClassID:
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case AMDGPU::GPRI32RegClassID:
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return &AMDGPU::R600_Reg32RegClass;
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default: return rc;
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}
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}
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unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
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return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
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}
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unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
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return GET_REG_INDEX(getEncodingValue(Reg));
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}
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const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
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}
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}
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const RegClassWeight &R600RegisterInfo::getRegClassWeight(
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const TargetRegisterClass *RC) const {
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return RCW;
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}
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bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
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assert(!TargetRegisterInfo::isVirtualRegister(Reg));
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switch (Reg) {
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case AMDGPU::OQAP:
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case AMDGPU::OQBP:
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case AMDGPU::AR_X:
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return false;
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default:
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return true;
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}
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}
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