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llvm-6502/lib/Target/R600
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Matt Arsenault d4786ed1de R600/SI: Match not instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205837 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 07:16:16 +00:00
..
InstPrinter Make methods static 2014-03-17 22:23:09 +00:00
MCTargetDesc Completely rewrite ELFObjectWriter::RecordRelocation. 2014-03-29 06:26:49 +00:00
TargetInfo Prune redundant dependencies in LLVMBuild.txt. 2013-12-11 00:30:57 +00:00
AMDGPU.h Fix known typos 2014-01-24 17:20:08 +00:00
AMDGPU.td R600: Recommit 199842: Add work-around for the CF stack entry HW bug 2014-01-23 16:18:02 +00:00
AMDGPUAsmPrinter.cpp R600/SI: Use correct dest register class for V_READFIRSTLANE_B32 2014-03-17 17:03:51 +00:00
AMDGPUAsmPrinter.h Add a default constructor to get deterministic behavior. 2013-12-05 16:21:17 +00:00
AMDGPUCallingConv.td R600: Use function inputs to represent data stored in gpr 2013-11-11 22:10:24 +00:00
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp R600: Take alignment into account when calculating the stack offset 2014-01-22 19:24:23 +00:00
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp Fix indentation 2014-03-11 00:01:27 +00:00
AMDGPUInstrInfo.h R600/SI: Implement spilling of SGPRs v5 2013-11-27 21:23:35 +00:00
AMDGPUInstrInfo.td R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
AMDGPUInstructions.td R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
AMDGPUIntrinsics.td R600: Add BFE, BFI, and BFM intrinsics to help with writing tests. 2014-03-31 18:21:18 +00:00
AMDGPUISelDAGToDAG.cpp R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
AMDGPUISelLowering.cpp R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
AMDGPUISelLowering.h R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
AMDGPUMachineFunction.cpp [weak vtables] Remove a bunch of weak vtables 2013-11-19 00:57:56 +00:00
AMDGPUMachineFunction.h [weak vtables] Remove a bunch of weak vtables 2013-11-19 00:57:56 +00:00
AMDGPUMCInstLower.cpp MachineInstr: introduce explicit_operands and implicit_operands ranges 2014-04-05 22:42:04 +00:00
AMDGPUMCInstLower.h
AMDGPURegisterInfo.cpp Make consistent use of MCPhysReg instead of uint16_t throughout the tree. 2014-04-04 05:16:06 +00:00
AMDGPURegisterInfo.h Make consistent use of MCPhysReg instead of uint16_t throughout the tree. 2014-04-04 05:16:06 +00:00
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp R600: Recommit 199842: Add work-around for the CF stack entry HW bug 2014-01-23 16:18:02 +00:00
AMDGPUSubtarget.h R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
AMDGPUTargetMachine.cpp R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU() 2014-03-21 15:51:57 +00:00
AMDGPUTargetMachine.h SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions 2013-07-27 00:01:07 +00:00
AMDGPUTargetTransformInfo.cpp Fix tabs 2014-04-04 20:13:08 +00:00
AMDILBase.td
AMDILCFGStructurizer.cpp R600: Don't viewCFG() under DEBUG() except on failure. 2014-03-24 20:29:02 +00:00
AMDILInstrInfo.td R600: Enable -verify-machineinstrs in some tests. 2013-10-01 19:32:38 +00:00
AMDILIntrinsicInfo.cpp
AMDILIntrinsicInfo.h
AMDILIntrinsics.td R600: Match sign_extend_inreg to BFE instructions 2014-03-17 18:58:11 +00:00
AMDILISelLowering.cpp R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp 2014-03-25 18:18:27 +00:00
AMDILRegisterInfo.td
CaymanInstructions.td R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
CMakeLists.txt [CMake] Let add_public_tablegen_target() provide intrinsics_gen, too. 2013-11-28 17:04:31 +00:00
EvergreenInstructions.td R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
LLVMBuild.txt Add proper dependencies to LLVMBuild.txt in llvm/lib. 2013-12-10 05:39:34 +00:00
Makefile
Processors.td R600: Recommit 199842: Add work-around for the CF stack entry HW bug 2014-01-23 16:18:02 +00:00
R600ClauseMergePass.cpp Fix known typos 2014-01-24 17:20:08 +00:00
R600ControlFlowFinalizer.cpp R600: Correctly handle vertex fetch clauses the precede ENDIFs 2014-01-23 18:49:31 +00:00
R600Defines.h Fix known typos 2014-01-24 17:20:08 +00:00
R600EmitClauseMarkers.cpp R600: Register R600EmitClauseMarkers pass 2013-12-11 17:51:41 +00:00
R600ExpandSpecialInstrs.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
R600InstrFormats.td R600: Use SchedModel enum for is{Trans,Vector}Only functions 2013-09-04 19:53:30 +00:00
R600InstrInfo.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
R600InstrInfo.h Fix known typos 2014-01-24 17:20:08 +00:00
R600Instructions.td R600: Reorganize tablegen instruction definitions 2014-03-24 16:07:25 +00:00
R600Intrinsics.td R600: Reenable llvm.R600.load.input/interp.input for compatibility 2013-11-12 16:26:47 +00:00
R600ISelLowering.cpp R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
R600ISelLowering.h R600/SI: Fix unreachable with a sext_in_reg to an illegal type. 2014-03-27 17:23:24 +00:00
R600MachineFunctionInfo.cpp [weak vtables] Remove a bunch of weak vtables 2013-11-19 00:57:56 +00:00
R600MachineFunctionInfo.h [weak vtables] Remove a bunch of weak vtables 2013-11-19 00:57:56 +00:00
R600MachineScheduler.cpp Factor MI-Sched in preparation for post-ra scheduling support. 2013-12-28 21:56:47 +00:00
R600MachineScheduler.h Factor MI-Sched in preparation for post-ra scheduling support. 2013-12-28 21:56:47 +00:00
R600OptimizeVectorRegisters.cpp Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing 2014-03-13 23:12:04 +00:00
R600Packetizer.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
R600RegisterInfo.cpp R600: Fix scheduling of instructions that use the LDS output queue 2013-11-15 00:12:45 +00:00
R600RegisterInfo.h R600: Fix scheduling of instructions that use the LDS output queue 2013-11-15 00:12:45 +00:00
R600RegisterInfo.td R600: Simplify handling of private address space 2013-10-22 18:19:10 +00:00
R600Schedule.td R600: Add local memory support via LDS 2013-06-28 15:47:08 +00:00
R600TextureIntrinsicsReplacer.cpp [Layering] Move InstVisitor.h into the IR library as it is pretty 2014-03-06 03:23:41 +00:00
R700Instructions.td R600: Reorganize tablegen instruction definitions 2014-03-24 16:07:25 +00:00
SIAnnotateControlFlow.cpp Add DEBUG_TYPE to SIAnnotateControlFlow 2014-02-03 22:58:05 +00:00
SIDefines.h R600/SI: Prefer SALU instructions for bit shift operations 2013-11-13 23:36:37 +00:00
SIFixSGPRCopies.cpp R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies 2014-04-07 19:45:45 +00:00
SIInsertWaits.cpp R600/SI: Add intrinsic for S_SENDMSG instruction 2014-01-27 07:20:44 +00:00
SIInstrFormats.td R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU() 2014-03-21 15:51:57 +00:00
SIInstrInfo.cpp R600/SI: Match not instruction. 2014-04-09 07:16:16 +00:00
SIInstrInfo.h R600/SI: Implement shouldConvertConstantLoadToIntImm 2014-03-31 19:54:27 +00:00
SIInstrInfo.td R600/SI: Lower 64-bit immediates using REG_SEQUENCE 2014-04-03 20:19:27 +00:00
SIInstructions.td R600/SI: Match not instruction. 2014-04-09 07:16:16 +00:00
SIIntrinsics.td R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions 2014-01-27 07:20:51 +00:00
SIISelLowering.cpp R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
SIISelLowering.h Change shouldSplitVectorElementType to better match the description. 2014-03-31 20:54:58 +00:00
SILowerControlFlow.cpp R600: avoid calling std::next on an iterator that might be end() 2014-03-28 13:52:56 +00:00
SIMachineFunctionInfo.cpp R600/SI: Implement spilling of SGPRs v5 2013-11-27 21:23:35 +00:00
SIMachineFunctionInfo.h R600/SI: Implement spilling of SGPRs v5 2013-11-27 21:23:35 +00:00
SIRegisterInfo.cpp R600/SI: Return the correct index for VGPRs in getHWRegIndex() 2014-03-31 14:01:52 +00:00
SIRegisterInfo.h R600/SI: Add support for private address space load/store 2013-11-13 23:36:50 +00:00
SIRegisterInfo.td R600/SI: Use correct dest register class for V_READFIRSTLANE_B32 2014-03-17 17:03:51 +00:00
SISchedule.td
SITypeRewriter.cpp [Layering] Move InstVisitor.h into the IR library as it is pretty 2014-03-06 03:23:41 +00:00