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The register index is stored in the low 8-bits of the encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205186 91177308-0d34-0410-b5e6-96231b3b80d8
132 lines
4.2 KiB
C++
132 lines
4.2 KiB
C++
//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SIRegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "SIInstrInfo.h"
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using namespace llvm;
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SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm)
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: AMDGPURegisterInfo(tm),
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TM(tm)
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{ }
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BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(AMDGPU::EXEC);
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Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
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const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(TM.getInstrInfo());
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TII->reserveIndirectRegisters(Reserved, MF);
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return Reserved;
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}
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unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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return RC->getNumRegs();
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}
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const TargetRegisterClass *
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SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
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switch (rc->getID()) {
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case AMDGPU::GPRF32RegClassID:
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return &AMDGPU::VReg_32RegClass;
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default: return rc;
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}
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}
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const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::VReg_32RegClass;
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}
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}
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unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
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return getEncodingValue(Reg) & 0xff;
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}
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const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
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assert(!TargetRegisterInfo::isVirtualRegister(Reg));
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const TargetRegisterClass *BaseClasses[] = {
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&AMDGPU::VReg_32RegClass,
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&AMDGPU::SReg_32RegClass,
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&AMDGPU::VReg_64RegClass,
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&AMDGPU::SReg_64RegClass,
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&AMDGPU::SReg_128RegClass,
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&AMDGPU::SReg_256RegClass
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};
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for (unsigned i = 0, e = sizeof(BaseClasses) /
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sizeof(const TargetRegisterClass*); i != e; ++i) {
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if (BaseClasses[i]->contains(Reg)) {
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return BaseClasses[i];
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}
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}
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return NULL;
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}
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bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
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if (!RC) {
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return false;
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}
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return !hasVGPRs(RC);
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}
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bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
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return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
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getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
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}
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const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
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const TargetRegisterClass *SRC) const {
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if (hasVGPRs(SRC)) {
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return SRC;
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} else if (SRC == &AMDGPU::SCCRegRegClass) {
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return &AMDGPU::VCCRegRegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
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return &AMDGPU::VReg_32RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
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return &AMDGPU::VReg_64RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
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return &AMDGPU::VReg_128RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
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return &AMDGPU::VReg_256RegClass;
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} else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
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return &AMDGPU::VReg_512RegClass;
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}
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return NULL;
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}
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const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
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const TargetRegisterClass *RC, unsigned SubIdx) const {
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if (SubIdx == AMDGPU::NoSubRegister)
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return RC;
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// If this register has a sub-register, we can safely assume it is a 32-bit
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// register, because all of SI's sub-registers are 32-bit.
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if (isSGPRClass(RC)) {
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return &AMDGPU::SGPR_32RegClass;
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} else {
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return &AMDGPU::VGPR_32RegClass;
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}
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}
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