mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
160 lines
4.7 KiB
LLVM
160 lines
4.7 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin > %t
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; RUN: FileCheck %s < %t
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; RUN: FileCheck %s < %t --check-prefix=CHECK-T2ADDRMODE
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%0 = type { i32, i32 }
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; CHECK-LABEL: f0:
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; CHECK: ldrexd
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define i64 @f0(i8* %p) nounwind readonly {
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entry:
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%ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p)
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%0 = extractvalue %0 %ldrexd, 1
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%1 = extractvalue %0 %ldrexd, 0
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%2 = zext i32 %0 to i64
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%3 = zext i32 %1 to i64
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%shl = shl nuw i64 %2, 32
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%4 = or i64 %shl, %3
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ret i64 %4
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}
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; CHECK-LABEL: f1:
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; CHECK: strexd
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define i32 @f1(i8* %ptr, i64 %val) nounwind {
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entry:
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%tmp4 = trunc i64 %val to i32
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%tmp6 = lshr i64 %val, 32
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%tmp7 = trunc i64 %tmp6 to i32
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%strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
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ret i32 %strexd
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}
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declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
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declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
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; CHECK-LABEL: test_load_i8:
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; CHECK: ldrexb r0, [r0]
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; CHECK-NOT: uxtb
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; CHECK-NOT: and
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define zeroext i8 @test_load_i8(i8* %addr) {
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%val = call i32 @llvm.arm.ldrex.p0i8(i8* %addr)
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%val8 = trunc i32 %val to i8
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ret i8 %val8
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}
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; CHECK-LABEL: test_load_i16:
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; CHECK: ldrexh r0, [r0]
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; CHECK-NOT: uxth
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; CHECK-NOT: and
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define zeroext i16 @test_load_i16(i16* %addr) {
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%val = call i32 @llvm.arm.ldrex.p0i16(i16* %addr)
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%val16 = trunc i32 %val to i16
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ret i16 %val16
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}
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; CHECK-LABEL: test_load_i32:
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; CHECK: ldrex r0, [r0]
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define i32 @test_load_i32(i32* %addr) {
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%val = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
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ret i32 %val
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}
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declare i32 @llvm.arm.ldrex.p0i8(i8*) nounwind readonly
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declare i32 @llvm.arm.ldrex.p0i16(i16*) nounwind readonly
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declare i32 @llvm.arm.ldrex.p0i32(i32*) nounwind readonly
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; CHECK-LABEL: test_store_i8:
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; CHECK-NOT: uxtb
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; CHECK: strexb r0, r1, [r2]
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define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
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%extval = zext i8 %val to i32
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%res = call i32 @llvm.arm.strex.p0i8(i32 %extval, i8* %addr)
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ret i32 %res
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}
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; CHECK-LABEL: test_store_i16:
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; CHECK-NOT: uxth
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; CHECK: strexh r0, r1, [r2]
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define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
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%extval = zext i16 %val to i32
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%res = call i32 @llvm.arm.strex.p0i16(i32 %extval, i16* %addr)
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ret i32 %res
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}
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; CHECK-LABEL: test_store_i32:
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; CHECK: strex r0, r1, [r2]
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define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
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%res = call i32 @llvm.arm.strex.p0i32(i32 %val, i32* %addr)
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ret i32 %res
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}
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declare i32 @llvm.arm.strex.p0i8(i32, i8*) nounwind
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declare i32 @llvm.arm.strex.p0i16(i32, i16*) nounwind
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declare i32 @llvm.arm.strex.p0i32(i32, i32*) nounwind
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; CHECK-LABEL: test_clear:
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; CHECK: clrex
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define void @test_clear() {
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call void @llvm.arm.clrex()
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ret void
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}
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declare void @llvm.arm.clrex() nounwind
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@base = global i32* null
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define void @excl_addrmode() {
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; CHECK-T2ADDRMODE-LABEL: excl_addrmode:
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%base1020 = load i32*, i32** @base
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%offset1020 = getelementptr i32, i32* %base1020, i32 255
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call i32 @llvm.arm.ldrex.p0i32(i32* %offset1020)
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call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1020)
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; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
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; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
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%base1024 = load i32*, i32** @base
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%offset1024 = getelementptr i32, i32* %base1024, i32 256
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call i32 @llvm.arm.ldrex.p0i32(i32* %offset1024)
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call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1024)
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; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024
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; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
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; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
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%base1 = load i32*, i32** @base
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%addr8 = bitcast i32* %base1 to i8*
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%offset1_8 = getelementptr i8, i8* %addr8, i32 1
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%offset1 = bitcast i8* %offset1_8 to i32*
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call i32 @llvm.arm.ldrex.p0i32(i32* %offset1)
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call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1)
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; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #1
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; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
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; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
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%local = alloca i8, i32 1024
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%local32 = bitcast i8* %local to i32*
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call i32 @llvm.arm.ldrex.p0i32(i32* %local32)
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call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32)
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; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
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; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
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; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
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ret void
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}
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; LLVM should know, even across basic blocks, that ldrex is setting the high
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; bits of its i32 to 0. There should be no zero-extend operation.
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define zeroext i8 @test_cross_block_zext_i8(i1 %tst, i8* %addr) {
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; CHECK: test_cross_block_zext_i8:
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; CHECK-NOT: uxtb
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; CHECK-NOT: and
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; CHECK: bx lr
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%val = call i32 @llvm.arm.ldrex.p0i8(i8* %addr)
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br i1 %tst, label %end, label %mid
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mid:
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ret i8 42
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end:
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%val8 = trunc i32 %val to i8
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ret i8 %val8
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}
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