mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
199 lines
6.1 KiB
LLVM
199 lines
6.1 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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; RUN: llc -mtriple=arm-eabi -mattr=+neon -regalloc=basic %s -o - | FileCheck %s
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define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vcgts8:
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;CHECK: vcgt.s8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = icmp sgt <8 x i8> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vcgts16:
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;CHECK: vcgt.s16
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = icmp sgt <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vcgts32:
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;CHECK: vcgt.s32
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%tmp3 = icmp sgt <2 x i32> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vcgtu8:
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;CHECK: vcgt.u8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = icmp ugt <8 x i8> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vcgtu16:
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;CHECK: vcgt.u16
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = icmp ugt <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vcgtu32:
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;CHECK: vcgt.u32
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%tmp3 = icmp ugt <2 x i32> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vcgtf32:
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;CHECK: vcgt.f32
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = fcmp ogt <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vcgtQs8:
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;CHECK: vcgt.s8
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = icmp sgt <16 x i8> %tmp1, %tmp2
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%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vcgtQs16:
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;CHECK: vcgt.s16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = icmp sgt <8 x i16> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vcgtQs32:
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;CHECK: vcgt.s32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = icmp sgt <4 x i32> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vcgtQu8:
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;CHECK: vcgt.u8
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = icmp ugt <16 x i8> %tmp1, %tmp2
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%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vcgtQu16:
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;CHECK: vcgt.u16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = icmp ugt <8 x i16> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vcgtQu32:
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;CHECK: vcgt.u32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = icmp ugt <4 x i32> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vcgtQf32:
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;CHECK: vcgt.f32
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vacgtf32:
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;CHECK: vacgt.f32
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vacgtQf32:
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;CHECK: vacgt.f32
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x i32> %tmp3
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}
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; rdar://7923010
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define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vcgt_zext:
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;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1
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;CHECK: vcgt.f32 [[Q1:q[0-9]+]]
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;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]]
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
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%tmp4 = zext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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declare <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vcgti8Z:
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;CHECK-NOT: vmov
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;CHECK-NOT: vmvn
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;CHECK: vcgt.s8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp3 = icmp sgt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vclti8Z:
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;CHECK-NOT: vmov
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;CHECK-NOT: vmvn
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;CHECK: vclt.s8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp3 = icmp slt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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