Evan Cheng ccb6976a69 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8		2009-01-02 05:35:45 +00:00
..
Alpha	Correct some thinkos in the expansion of ADD/SUB	2008-11-12 08:23:26 +00:00
ARM	Clean up some ARM GV asm printing out; minor fixes to match what gcc does.	2008-12-06 02:00:55 +00:00
CBackend
CellSPU	Fix PR3274: when promoting the condition of a BRCOND node,	2009-01-01 15:52:00 +00:00
CPP
Generic	Revert the changes in this testcase until Anton can fix them.	2008-12-24 05:23:34 +00:00
IA64
Mips	Fix PR2667: add soft float support for sint_to_fp/uint_to_fp	2008-11-10 17:36:26 +00:00
PowerPC	rename a file to follow naming conventions.	2009-01-02 01:52:35 +00:00
SPARC
X86	Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.	2009-01-02 05:35:45 +00:00
XCore	Add support for ISD::TRAP to the XCore backend	2008-12-03 10:59:16 +00:00