Hao Liu ae6c659d34 [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208955 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-16 09:39:02 +00:00
..
AArch64	Implement global merge optimization for global variables.	2014-05-15 23:45:42 +00:00
ARM	ARM: add some integer/floating point conversion libcalls	2014-05-16 05:41:33 +00:00
ARM64	[ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R.	2014-05-16 09:39:02 +00:00
CPP
Generic
Hexagon	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
Inputs
Mips	Finish materialize for ints	2014-05-15 21:54:15 +00:00
MSP430
NVPTX
PowerPC	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
R600	R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0	2014-05-15 14:41:54 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	llvm/test/CodeGen/X86/combine-sse41-intrinsics.ll: Add explicit triple.	2014-05-15 15:45:31 +00:00
XCore