Quentin Colombet af1cd03764 [AArch64][LoadStoreOptimizer] Form LDPSW when possible. ... This patch adds the missing LD[U]RSW variants to the load store optimizer, so that we generate LDPSW when possible. <rdar://problem/19583480> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226978 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-24 01:25:54 +00:00
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AArch64	[AArch64][LoadStoreOptimizer] Form LDPSW when possible.	2015-01-24 01:25:54 +00:00
ARM	This patch fixes issue with lowering below mentioned pattern :-	2015-01-23 09:10:03 +00:00
CPP
Generic
Hexagon	[Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns.	2015-01-21 18:13:15 +00:00
Inputs
Mips	[mips] Add registers and ALL check prefix to octeon test case.	2015-01-20 16:14:02 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add r2 as an operand for all calls under both PPC64 ELF V1 and V2	2015-01-19 07:20:27 +00:00
R600	R600/SI: Emit .hsa.version section for amdhsa OS	2015-01-23 23:59:08 +00:00
SPARC
SystemZ
Thumb	IR: Move MDLocation into place	2015-01-14 22:27:36 +00:00
Thumb2
X86	Fix assertion when C++ EH filters are present in functions using SEH	2015-01-23 23:51:25 +00:00
XCore