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https://github.com/c64scene-ar/llvm-6502.git
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3dd951e842
- Adds support for inserting vzerouppers before tail-calls. This is enabled implicitly by having MachineInstr::copyImplicitOps preserve regmask operands, which allows VZeroUpperInserter to see where tail-calls use vector registers. - Fixes a bug that caused the previous version of this optimization to miss some vzeroupper insertion points in loops. (Loops-with-vector-code that followed loops-without-vector-code were mistakenly overlooked by the previous version). - New algorithm never revisits instructions. Fixes <rdar://problem/16228798> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204021 91177308-0d34-0410-b5e6-96231b3b80d8
103 lines
3.5 KiB
LLVM
103 lines
3.5 KiB
LLVM
; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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declare i32 @foo()
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declare <4 x float> @do_sse(<4 x float>)
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declare <8 x float> @do_avx(<8 x float>)
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declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
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@x = common global <4 x float> zeroinitializer, align 16
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@g = common global <8 x float> zeroinitializer, align 32
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;; Basic checking - don't emit any vzeroupper instruction
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; CHECK: _test00
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define <4 x float> @test00(<4 x float> %a, <4 x float> %b) nounwind uwtable ssp {
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entry:
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; CHECK-NOT: vzeroupper
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%add.i = fadd <4 x float> %a, %b
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%call3 = call <4 x float> @do_sse(<4 x float> %add.i) nounwind
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; CHECK: ret
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ret <4 x float> %call3
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}
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;; Check parameter 256-bit parameter passing
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; CHECK: _test01
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define <8 x float> @test01(<4 x float> %a, <4 x float> %b, <8 x float> %c) nounwind uwtable ssp {
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entry:
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%tmp = load <4 x float>* @x, align 16
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; CHECK: vzeroupper
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; CHECK-NEXT: callq _do_sse
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%call = tail call <4 x float> @do_sse(<4 x float> %tmp) nounwind
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store <4 x float> %call, <4 x float>* @x, align 16
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; CHECK-NOT: vzeroupper
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; CHECK: callq _do_sse
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%call2 = tail call <4 x float> @do_sse(<4 x float> %call) nounwind
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store <4 x float> %call2, <4 x float>* @x, align 16
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; CHECK: ret
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ret <8 x float> %c
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}
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;; Check that vzeroupper is emitted for tail calls.
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; CHECK: _test02
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define <4 x float> @test02(<8 x float> %a, <8 x float> %b) nounwind uwtable ssp {
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entry:
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%add.i = fadd <8 x float> %a, %b
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%add.low = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %add.i, i8 0)
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; CHECK: vzeroupper
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; CHECK: jmp _do_sse
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%call3 = tail call <4 x float> @do_sse(<4 x float> %add.low) nounwind
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ret <4 x float> %call3
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}
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;; Test the pass convergence and also that vzeroupper is only issued when necessary,
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;; for this function it should be only once
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; CHECK: _test03
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define <4 x float> @test03(<4 x float> %a, <4 x float> %b) nounwind uwtable ssp {
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entry:
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%add.i = fadd <4 x float> %a, %b
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br label %while.cond
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while.cond:
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%call = tail call i32 @foo()
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%tobool = icmp eq i32 %call, 0
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br i1 %tobool, label %for.body, label %while.cond
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for.body:
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; CHECK: LBB
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; CHECK-NOT: vzeroupper
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%i.018 = phi i32 [ 0, %while.cond ], [ %1, %for.body ]
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%c.017 = phi <4 x float> [ %add.i, %while.cond ], [ %call14, %for.body ]
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; CHECK: callq _do_sse
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%call5 = tail call <4 x float> @do_sse(<4 x float> %c.017) nounwind
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; CHECK-NEXT: callq _do_sse
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%call7 = tail call <4 x float> @do_sse(<4 x float> %call5) nounwind
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%tmp11 = load <8 x float>* @g, align 32
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%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %tmp11, i8 1) nounwind
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; CHECK: vzeroupper
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; CHECK-NEXT: callq _do_sse
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%call14 = tail call <4 x float> @do_sse(<4 x float> %0) nounwind
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%1 = add nsw i32 %i.018, 1
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%exitcond = icmp eq i32 %1, 4
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret <4 x float> %call14
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}
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;; Check that we also perform vzeroupper when we return from a function.
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; CHECK: _test04
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define <4 x float> @test04(<4 x float> %a, <4 x float> %b) nounwind uwtable ssp {
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entry:
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%shuf = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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; CHECK-NOT: vzeroupper
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; CHECK: call
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%call = call <8 x float> @do_avx(<8 x float> %shuf) nounwind
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%shuf2 = shufflevector <8 x float> %call, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK: vzeroupper
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; CHECK: ret
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ret <4 x float> %shuf2
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}
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