llvm-6502/test/CodeGen
Duncan Sands af7852f094 Check that running the DAG combiner between type
and operation legalization does something useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60108 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-26 16:44:30 +00:00
..
Alpha Correct some thinkos in the expansion of ADD/SUB 2008-11-12 08:23:26 +00:00
ARM - Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction. 2008-11-20 02:32:35 +00:00
CBackend
CellSPU CellSPU: 2008-11-25 17:29:43 +00:00
CPP
Generic Test add-with-overflow with fast ISel. 2008-11-24 05:23:38 +00:00
IA64
Mips Fix PR2667: add soft float support for sint_to_fp/uint_to_fp 2008-11-10 17:36:26 +00:00
PowerPC Check that running the DAG combiner between type 2008-11-26 16:44:30 +00:00
SPARC
X86 This adds in some code (currently disabled unless you pass 2008-11-26 02:00:14 +00:00
XCore Reapply r59464, this time using the correct type 2008-11-18 09:15:03 +00:00