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llvm-6502/lib/Target/ARM/MCTargetDesc
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Evan Cheng 97a454317a - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2 
instructions.
- However, it does support dmb, dsb, isb, mrs, and msr.
rdar://11331541


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 01:27:19 +00:00
..
ARMAddressingModes.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
ARMAsmBackend.cpp ARM: Thumb ldr(literal) base address alignment is 32-bits. 2012-04-26 20:48:12 +00:00
ARMBaseInfo.h ARM more NEON VLD/VST composite physical register refactoring. 2012-03-06 23:10:38 +00:00
ARMELFObjectWriter.cpp Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch. 2012-03-30 09:15:32 +00:00
ARMFixupKinds.h Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch. 2012-03-30 09:15:32 +00:00
ARMMachObjectWriter.cpp Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch. 2012-03-30 09:15:32 +00:00
ARMMCAsmInfo.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
ARMMCAsmInfo.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
ARMMCCodeEmitter.cpp Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. 2012-04-25 18:00:18 +00:00
ARMMCExpr.cpp Convert assert(0) to llvm_unreachable 2012-02-07 02:50:20 +00:00
ARMMCExpr.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
ARMMCTargetDesc.cpp - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2 2012-04-27 01:27:19 +00:00
ARMMCTargetDesc.h If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume 2012-04-26 01:13:36 +00:00
CMakeLists.txt Hopefully fix the cmake build. 2011-12-22 01:11:01 +00:00
LLVMBuild.txt LLVMBuild: Remove trailing newline, which irked me. 2011-12-12 19:48:00 +00:00
Makefile