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https://github.com/c64scene-ar/llvm-6502.git
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5c9bb7119a
Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
755 B
LLVM
23 lines
755 B
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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; FUNC-LABEL: @i32_mul24
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; Signed 24-bit multiply is not supported on pre-Cayman GPUs.
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; EG: MULLO_INT
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; Make sure we are not masking the inputs
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; CM-NOT: AND
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; CM: MUL_INT24
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; SI-NOT: AND
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; SI: V_MUL_I32_I24
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define void @i32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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entry:
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%0 = shl i32 %a, 8
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%a_24 = ashr i32 %0, 8
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%1 = shl i32 %b, 8
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%b_24 = ashr i32 %1, 8
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%2 = mul i32 %a_24, %b_24
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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