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https://github.com/c64scene-ar/llvm-6502.git
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5c9bb7119a
Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
806 B
LLVM
25 lines
806 B
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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; FIXME: Move this test into mul_uint24.ll once i64 mul is supported.
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; XFAIL: *
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; Multiply with 24-bit inputs and 64-bit output
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; FUNC_LABEL: @mul24_i64
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; EG; MUL_UINT24
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; EG: MULHI
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; SI: V_MUL_U32_U24
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; FIXME: SI support 24-bit mulhi
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; SI: V_MUL_HI_U32
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define void @mul24_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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entry:
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%0 = shl i64 %a, 40
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%a_24 = lshr i64 %0, 40
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%1 = shl i64 %b, 40
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%b_24 = lshr i64 %1, 40
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%2 = mul i64 %a_24, %b_24
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store i64 %2, i64 addrspace(1)* %out
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ret void
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}
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