llvm-6502/test/CodeGen
Jakob Stoklund Olesen 3247af2949 Add <imp-def> operands when reloading into physregs.
When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register.  When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06 02:48:17 +00:00
..
ARM Add <imp-def> operands when reloading into physregs. 2012-03-06 02:48:17 +00:00
CBackend
CellSPU
CPP
Generic
Hexagon
MBlaze
Mips Fix bugs which were introduced when support for base+index floating point loads 2012-03-01 22:12:30 +00:00
MSP430
PowerPC Test the section specification. 2012-02-27 20:42:19 +00:00
PTX
SPARC
Thumb
Thumb2 Enable ARM base pointer when calling functions with large arguments. 2012-02-28 01:15:01 +00:00
X86 Remove a test case that no longer makes sense. 2012-03-05 19:10:13 +00:00
XCore