Matthias Braun b0d6c659b7 X86: Reject register operands with obvious type mismatches. ... While we have some code to transform specification like {ax} into {eax}/{rax} if the operand type isn't 16bit, we should reject cases where there is no sane way to do this, like the i128 type in the example. Related to rdar://21042280 Differential Revision: http://reviews.llvm.org/D10260 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239309 91177308-0d34-0410-b5e6-96231b3b80d8		2015-06-08 16:56:23 +00:00
..
Analysis	Minor refactoring of GEP handling in isDereferenceablePointer	2015-06-08 11:58:13 +00:00
AsmParser	Fix doxygen comments. NFC	2015-06-07 06:40:24 +00:00
Bitcode	Use early return idiom. NFC	2015-06-06 20:44:53 +00:00
CodeGen	Fix assertion failure in global-merge with unused ConstantExpr	2015-06-08 16:55:31 +00:00
DebugInfo
ExecutionEngine	[Mips64][mcjit] Add R_MIPS_PC32 relocation	2015-06-08 14:10:23 +00:00
Fuzzer
IR	[AsmWriter] Rewrite module asm printing using StringRef::split.	2015-06-07 13:59:33 +00:00
IRReader
LineEditor
Linker
LTO
MC	[MC] Common symbols weren't being checked for redeclaration which allowed an assembly file to generate an assertion in setCommon(): !isCommon(). This change allows redeclaration as long as the size and alignment match exactly, otherwise report a fatal error.	2015-06-06 20:12:40 +00:00
Object	Fix Windows build.	2015-06-08 02:43:32 +00:00
Option
Passes
ProfileData
Support	TargetParser: Fix comments in enum(s) introduced in r239150. [-Wdocumentation]	2015-06-06 01:41:35 +00:00
TableGen
Target	X86: Reject register operands with obvious type mismatches.	2015-06-08 16:56:23 +00:00
Transforms	[LoopVectorize] Teach Loop Vectorizor about interleaved memory accesses.	2015-06-08 06:39:56 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile