Johnny Chen e68d8ec252 It used to be that t_addrmode_s4 was used for both: ... o A8.6.195 STR (register) -- Encoding T1 o A8.6.193 STR (immediate, Thumb) -- Encoding T1 It has been changed so that now they use different addressing modes and thus different MC representation (Operand Infos). Modify the disassembler to reflect the change, and add relevant tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127833 91177308-0d34-0410-b5e6-96231b3b80d8		2011-03-17 22:04:05 +00:00
..
ARM	Roll r127459 back in:	2011-03-11 21:52:04 +00:00
AsmParser	Move arch specific tests in arch specific directories.	2011-02-24 19:06:27 +00:00
COFF	Don't use PadSectionToAlignment on windows.	2010-12-06 03:03:44 +00:00
Disassembler	It used to be that t_addrmode_s4 was used for both:	2011-03-17 22:04:05 +00:00
ELF	Fix handling of @IDNTPOFF relocations, they need to get STT_TLS.	2011-03-17 00:35:10 +00:00
MachO	MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't have	2011-03-17 16:25:24 +00:00
MBlaze	Teach the MBlaze asm parser how to parse special purpose register names.	2010-12-20 20:43:24 +00:00
X86	Followup to r126970: add 64-bit encoding tests for str with reg operand.	2011-03-04 04:06:47 +00:00