llvm-6502/lib/CodeGen/SelectionDAG
Chris Lattner b14ab8a10d Teach the dag combiner to turn a truncate/sign_extend pair into a sextinreg
when the types match up.  This allows the X86 backend to compile:

sbyte %toggle_value(sbyte* %tmp.1) {
        %tmp.2 = load sbyte* %tmp.1
        ret sbyte %tmp.2
}

to this:

_toggle_value:
        mov %EAX, DWORD PTR [%ESP + 4]
        movsx %EAX, BYTE PTR [%EAX]
        ret

instead of this:

_toggle_value:
        mov %EAX, DWORD PTR [%ESP + 4]
        movsx %EAX, BYTE PTR [%EAX]
        movsx %EAX, %AL
        ret

noticed in Shootout/objinst.

-Chris


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24630 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-07 07:11:03 +00:00
..
DAGCombiner.cpp Teach the dag combiner to turn a truncate/sign_extend pair into a sextinreg 2005-12-07 07:11:03 +00:00
LegalizeDAG.cpp Teach the SelectionDAG ISel how to turn ConstantPacked values into 2005-12-06 06:18:55 +00:00
Makefile
ScheduleDAG.cpp Support multiple ValueTypes per RegisterClass, needed for upcoming vector 2005-12-01 04:51:06 +00:00
SelectionDAG.cpp Teach the SelectionDAG ISel how to turn ConstantPacked values into 2005-12-06 06:18:55 +00:00
SelectionDAGISel.cpp Teach the SelectionDAG ISel how to turn ConstantPacked values into 2005-12-06 06:18:55 +00:00
SelectionDAGPrinter.cpp Added an index field to GlobalAddressSDNode so it can represent X+12, etc. 2005-11-30 02:04:11 +00:00
TargetLowering.cpp Add the majority of the vector machien value types we expect to support, 2005-11-29 05:45:29 +00:00