Tom Stellard 96b5670cf4 R600/SI: fix MIMG writemask adjustement ...

This fixes piglit:
- shaders/glsl-fs-texture2d-masked
- shaders/glsl-fs-texture2d-masked-4

Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193222 91177308-0d34-0410-b5e6-96231b3b80d8

2013-10-23 02:53:47 +00:00

..

AArch64

[AArch64] Add the constraint to NEON scalar mla/mls instructions.

2013-10-21 20:11:47 +00:00

ARM

17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets

2013-10-17 19:52:05 +00:00

CPP

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Generic

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Hexagon

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Inputs

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Mips

[mips][msa] Fix definition of SLD instruction.

2013-10-21 11:47:56 +00:00

MSP430

Fix MSP430 calling convention to match MSPGCC

2013-10-15 08:19:39 +00:00

NVPTX

[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc

2013-10-11 12:39:39 +00:00

PowerPC

Update PPC loop tests after SCEV non-unit-stride checkin r193015.

2013-10-19 00:14:04 +00:00

R600

R600/SI: fix MIMG writemask adjustement

2013-10-23 02:53:47 +00:00

SPARC

[Sparc] Disable tail call optimization for sparc64.

2013-10-09 12:50:39 +00:00

SystemZ

Replace sra with srl if a single sign bit is required

2013-10-17 11:16:57 +00:00

Thumb

17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets

2013-10-17 19:52:05 +00:00

Thumb2

MachineSink: Fix and tweak critical-edge breaking heuristic.

2013-10-14 16:57:17 +00:00

X86

AVX-512: aligned / unaligned load and store for 512-bit integer vectors.

2013-10-22 09:19:28 +00:00

XCore

XCore target fix bug in emitArrayBound() causing segmentation fault

2013-10-11 10:27:13 +00:00