llvm-6502/test/CodeGen
Benjamin Kramer b20a8fc8a6 X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039)
This tends to happen a lot with bitfield code generated by clang. A simple example for x86_64 is
uint64_t foo(uint64_t x) { return (x&1) << 42; }
which used to compile into bloated code:
	shlq	$42, %rdi               ## encoding: [0x48,0xc1,0xe7,0x2a]
	movabsq	$4398046511104, %rax    ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00]
	andq	%rdi, %rax              ## encoding: [0x48,0x21,0xf8]
	ret                             ## encoding: [0xc3]

with this patch we can fold the immediate into the and:
	andq	$1, %rdi                ## encoding: [0x48,0x83,0xe7,0x01]
	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
	shlq	$42, %rax               ## encoding: [0x48,0xc1,0xe0,0x2a]
	ret                             ## encoding: [0xc3]

It's possible to save another byte by using 'andl' instead of 'andq' but I currently see no way of doing
that without making this code even more complicated. See the TODOs in the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 15:30:40 +00:00
..
Alpha If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0. 2010-12-06 22:39:26 +00:00
ARM Fix DWARF description of Q registers. 2011-04-21 23:22:35 +00:00
Blackfin Don't completely eliminate identity copies that also modify super register liveness. 2011-03-31 17:55:25 +00:00
CBackend
CellSPU don't test for codegen of 'store undef' 2011-04-09 02:31:26 +00:00
CPP
Generic Un-XFAIL this test for ARM. <rdar://problem/7662569> 2011-04-20 21:47:45 +00:00
MBlaze Add scheduling information for the MBlaze backend. 2011-04-11 22:31:52 +00:00
Mips Make tests register allocation independent again. 2011-04-19 00:14:43 +00:00
MSP430 Enhance ComputeMaskedBits to know that aligned frameindexes 2011-02-13 22:25:43 +00:00
PowerPC These tests no longer require linear scan because reserved register coalescing is now universal. 2011-04-05 21:40:41 +00:00
PTX ptx: fix parameter ordering 2011-04-21 10:56:58 +00:00
SPARC These tests no longer require linear scan because reserved register coalescing is now universal. 2011-04-05 21:40:41 +00:00
SystemZ Fix SystemZ tests 2011-03-31 23:02:12 +00:00
Thumb Make tests register allocation independent again. 2011-04-19 00:14:43 +00:00
Thumb2 In Thumb2 mode, lower frame indix references to: 2011-04-22 01:42:52 +00:00
X86 X86: Try to use a smaller encoding by transforming (X << C1) & C2 into (X & (C2 >> C1)) & C1. (Part of PR5039) 2011-04-22 15:30:40 +00:00
XCore Fix Mips, Sparc, and XCore tests that were dependent on register allocation. 2011-03-31 18:42:43 +00:00