llvm-6502/lib/Target/Sparc
Jakob Stoklund Olesen ddb14ce76c Passing arguments to varags functions under the SPARC v9 ABI.
Arguments after the fixed arguments never use the floating point
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-21 21:36:49 +00:00
..
MCTargetDesc Add target flags to SPARC address operands. 2013-04-14 01:33:32 +00:00
TargetInfo
CMakeLists.txt
DelaySlotFiller.cpp
FPMover.cpp
LLVMBuild.txt
Makefile
README.txt
Sparc.h
Sparc.td
SparcAsmPrinter.cpp Use target flags for printing SPARC asm operands. 2013-04-14 04:35:19 +00:00
SparcCallingConv.td Complete formal arguments for the SPARC v9 64-bit ABI. 2013-04-06 18:32:12 +00:00
SparcFrameLowering.cpp Compute correct frame sizes for SPARC v9 64-bit frames. 2013-04-09 04:37:47 +00:00
SparcFrameLowering.h Compute correct frame sizes for SPARC v9 64-bit frames. 2013-04-09 04:37:47 +00:00
SparcInstr64Bit.td Add 64-bit multiply and divide instructions for SPARC v9. 2013-04-16 02:57:02 +00:00
SparcInstrFormats.td Use i32 for all SPARC shift amounts, even in 64-bit mode. 2013-04-14 05:48:50 +00:00
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td Fix the SETHIimm pattern for 64-bit code. 2013-04-21 21:18:03 +00:00
SparcISelDAGToDAG.cpp Add 64-bit multiply and divide instructions for SPARC v9. 2013-04-16 02:57:02 +00:00
SparcISelLowering.cpp Passing arguments to varags functions under the SPARC v9 ABI. 2013-04-21 21:36:49 +00:00
SparcISelLowering.h Use i32 for all SPARC shift amounts, even in 64-bit mode. 2013-04-14 05:48:50 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcRegisterInfo.cpp SPARC v9 stack pointer bias. 2013-04-06 21:38:57 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td Add 64-bit compare + branch for SPARC v9. 2013-04-03 04:41:44 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp
SparcSubtarget.h SPARC v9 stack pointer bias. 2013-04-06 21:38:57 +00:00
SparcTargetMachine.cpp
SparcTargetMachine.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support