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https://github.com/c64scene-ar/llvm-6502.git
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b2f47c6a34
ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR. For example, given the following sequence of dag nodes: i32 C = Constant<1> v4i32 V = BUILD_VECTOR C, C, C, C v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1 The SIGN_EXTEND_INREG node can be folded into a build_vector since the vector in input is a BUILD_VECTOR of constants. The optimized sequence is: i32 C = Constant<-1> v4i32 Result = BUILD_VECTOR C, C, C, C git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198084 91177308-0d34-0410-b5e6-96231b3b80d8
134 lines
3.7 KiB
LLVM
134 lines
3.7 KiB
LLVM
; RUN: llc -march=x86-64 -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
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; Verify that we don't emit packed vector shifts instructions if the
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; condition used by the vector select is a vector of constants.
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test1
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test4
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: movaps %xmm1, %xmm0
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; CHECK: ret
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define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
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%1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test5
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test6
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test7
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test8
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test9
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: movaps %xmm1, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test10
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test11
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test12
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
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%1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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