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9993b88f06
Pointed out by Javier Martinez (who also provided a patch). Since this logic is not used on (for example) x86, I guess nobody noticed. Tested by generating SHL, SRL, SRA on various choices of i64 for all possible shift amounts, and comparing with gcc. Since I did this on x86-32, I had to force the use of ExpandShiftWithUnknownAmountBit. What I'm saying here is that I don't have a testcase I can add to the repository. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90482 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
CallingConvLower.cpp | ||
CMakeLists.txt | ||
DAGCombiner.cpp | ||
FastISel.cpp | ||
FunctionLoweringInfo.cpp | ||
FunctionLoweringInfo.h | ||
InstrEmitter.cpp | ||
InstrEmitter.h | ||
LegalizeDAG.cpp | ||
LegalizeFloatTypes.cpp | ||
LegalizeIntegerTypes.cpp | ||
LegalizeTypes.cpp | ||
LegalizeTypes.h | ||
LegalizeTypesGeneric.cpp | ||
LegalizeVectorOps.cpp | ||
LegalizeVectorTypes.cpp | ||
Makefile | ||
ScheduleDAGFast.cpp | ||
ScheduleDAGList.cpp | ||
ScheduleDAGRRList.cpp | ||
ScheduleDAGSDNodes.cpp | ||
ScheduleDAGSDNodes.h | ||
SelectionDAG.cpp | ||
SelectionDAGBuilder.cpp | ||
SelectionDAGBuilder.h | ||
SelectionDAGISel.cpp | ||
SelectionDAGPrinter.cpp | ||
TargetLowering.cpp |