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https://github.com/c64scene-ar/llvm-6502.git
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6393b3a677
This patch checks for DAG patterns that are an add or a sub followed by a compare on 16 and 8 bit inputs. Since AArch64 does not support those types natively they are legalized into 32 bit values, which means that mask operations are inserted into the DAG to emulate overflow behaviour. In many cases those masks do not change the result of the processing and just introduce a dependent operation, often in the middle of a hot loop. This patch detects the relevent DAG patterns and then tests to see if the transforms are equivalent with and without the mask, removing the mask if possible. The exact mechanism of this patch was discusses in http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-July/074444.html There is a reasonably good chance there are missed oppurtunities due to similiar (but not identical) DAG patterns that could be funneled into this test, adding them should be simple if we see test cases. Tests included. rdar://13754426 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216776 91177308-0d34-0410-b5e6-96231b3b80d8
270 lines
5.4 KiB
LLVM
270 lines
5.4 KiB
LLVM
; RUN: llc -O0 -fast-isel=false -mtriple=arm64-apple-darwin < %s | FileCheck %s
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@board = common global [400 x i8] zeroinitializer, align 1
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@next_string = common global i32 0, align 4
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@string_number = common global [400 x i32] zeroinitializer, align 4
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; Function Attrs: nounwind ssp
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define void @new_position(i32 %pos) {
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entry:
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%idxprom = sext i32 %pos to i64
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%arrayidx = getelementptr inbounds [400 x i8]* @board, i64 0, i64 %idxprom
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%tmp = load i8* %arrayidx, align 1
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%.off = add i8 %tmp, -1
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%switch = icmp ult i8 %.off, 2
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br i1 %switch, label %if.then, label %if.end
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if.then: ; preds = %entry
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%tmp1 = load i32* @next_string, align 4
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%arrayidx8 = getelementptr inbounds [400 x i32]* @string_number, i64 0, i64 %idxprom
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store i32 %tmp1, i32* %arrayidx8, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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; CHECK-LABEL: new_position
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_0(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 74
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%1 = icmp ult i8 %0, -20
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_0
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; CHECK: and
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; CHECK: ret
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}
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define zeroext i1 @test8_1(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 246
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%1 = icmp uge i8 %0, 90
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_1
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_2(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 227
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%1 = icmp ne i8 %0, 179
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_2
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_3(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 201
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%1 = icmp eq i8 %0, 154
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_3
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_4(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, -79
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%1 = icmp ne i8 %0, -40
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_4
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_5(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 133
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%1 = icmp uge i8 %0, -105
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_5
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; CHECK: and
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; CHECK: ret
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}
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define zeroext i1 @test8_6(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, -58
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%1 = icmp uge i8 %0, 155
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_6
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; CHECK: and
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; CHECK: ret
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}
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define zeroext i1 @test8_7(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 225
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%1 = icmp ult i8 %0, 124
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_7
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test8_8(i8 zeroext %x) align 2 {
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entry:
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%0 = add i8 %x, 190
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%1 = icmp uge i8 %0, 1
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test8_8
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test16_0(i16 zeroext %x) align 2 {
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entry:
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%0 = add i16 %x, -46989
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%1 = icmp ne i16 %0, -41903
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test16_0
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test16_2(i16 zeroext %x) align 2 {
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entry:
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%0 = add i16 %x, 16882
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%1 = icmp ule i16 %0, -24837
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test16_2
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; CHECK: and
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; CHECK: ret
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}
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define zeroext i1 @test16_3(i16 zeroext %x) align 2 {
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entry:
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%0 = add i16 %x, 29283
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%1 = icmp ne i16 %0, 16947
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test16_3
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test16_4(i16 zeroext %x) align 2 {
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entry:
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%0 = add i16 %x, -35551
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%1 = icmp uge i16 %0, 15677
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test16_4
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; CHECK: and
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; CHECK: ret
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}
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define zeroext i1 @test16_5(i16 zeroext %x) align 2 {
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entry:
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%0 = add i16 %x, -25214
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%1 = icmp ne i16 %0, -1932
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test16_5
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test16_6(i16 zeroext %x) align 2 {
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entry:
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%0 = add i16 %x, -32194
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%1 = icmp uge i16 %0, -41215
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test16_6
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; CHECK-NOT: and
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; CHECK: ret
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}
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define zeroext i1 @test16_7(i16 zeroext %x) align 2 {
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entry:
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%0 = add i16 %x, 9272
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%1 = icmp uge i16 %0, -42916
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test16_7
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; CHECK: and
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; CHECK: ret
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}
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define zeroext i1 @test16_8(i16 zeroext %x) align 2 {
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entry:
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%0 = add i16 %x, -63749
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%1 = icmp ne i16 %0, 6706
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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; CHECK-LABEL: test16_8
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; CHECK-NOT: and
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; CHECK: ret
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}
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