llvm-6502/lib/Target/X86
Chris Lattner 3d36a9f6f4 Several things:
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly.  The port number really
   *is* a 16-bit value, but the patterns should only match if the number
   is 0-255.  Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
   i8, not an i16 as they were believed to be before.  This previous fib
   stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24599 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-05 02:40:25 +00:00
..
.cvsignore ignore generated files 2004-11-21 00:01:54 +00:00
Makefile initial step at adding a dag-to-dag isel for X86 backend. Patch contributed 2005-11-16 01:54:32 +00:00
README.txt add a note 2005-12-02 00:11:20 +00:00
X86.h Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch 2005-11-15 00:40:23 +00:00
X86.td Get closer to fully working scalar FP in SSE regs. This gets singlesource 2005-07-15 00:38:55 +00:00
X86AsmPrinter.cpp Use HasDotTypeDotSizeDirective instead of forELF 2005-11-21 23:06:54 +00:00
X86AsmPrinter.h Use HasDotTypeDotSizeDirective instead of forELF 2005-11-21 23:06:54 +00:00
X86ATTAsmPrinter.cpp No longer track value types for asm printer operands, and remove them as 2005-11-30 18:54:35 +00:00
X86ATTAsmPrinter.h No longer track value types for asm printer operands, and remove them as 2005-11-30 18:54:35 +00:00
X86CodeEmitter.cpp Refactor things a bit to allow the ELF code emitter to run the X86 machine code emitter 2005-07-11 05:17:48 +00:00
X86ELFWriter.cpp Refactor things a bit to allow the ELF code emitter to run the X86 machine code emitter 2005-07-11 05:17:48 +00:00
X86FloatingPoint.cpp Adjust to new livevars interface 2005-08-23 23:41:14 +00:00
X86InstrBuilder.h * Remove trailing whitespace 2005-04-21 23:38:14 +00:00
X86InstrInfo.cpp Properly split f32 and f64 into separate register classes for scalar sse fp 2005-10-14 22:06:00 +00:00
X86InstrInfo.h Eliminate tabs and trailing spaces. 2005-07-27 05:53:44 +00:00
X86InstrInfo.td Several things: 2005-12-05 02:40:25 +00:00
X86IntelAsmPrinter.cpp No longer track value types for asm printer operands, and remove them as 2005-11-30 18:54:35 +00:00
X86IntelAsmPrinter.h Fix a typo in my latest change 2005-11-30 18:57:39 +00:00
X86ISelDAGToDAG.cpp Proper support for shifts with register shift value. 2005-12-01 00:43:55 +00:00
X86ISelLowering.cpp No targets support line number info yet. 2005-11-29 06:16:21 +00:00
X86ISelLowering.h The second patch of X86 support for read cycle counter. 2005-11-20 21:41:10 +00:00
X86ISelPattern.cpp Fix PR672 another way which should be more robust 2005-12-04 06:03:50 +00:00
X86JITInfo.cpp update interface 2005-07-22 20:49:37 +00:00
X86JITInfo.h turn off GOT on archs that didn't use it (not that it appeard to harm them much with it on) 2005-07-29 23:32:02 +00:00
X86PeepholeOpt.cpp Eliminate all remaining tabs and trailing spaces. 2005-07-27 06:12:32 +00:00
X86RegisterInfo.cpp Properly split f32 and f64 into separate register classes for scalar sse fp 2005-10-14 22:06:00 +00:00
X86RegisterInfo.h Pass extra regclasses into spilling code 2005-09-30 01:29:42 +00:00
X86RegisterInfo.td Support multiple ValueTypes per RegisterClass, needed for upcoming vector 2005-12-01 04:51:06 +00:00
X86Relocations.h * Remove trailing whitespace 2005-04-21 23:38:14 +00:00
X86Subtarget.cpp Simplify the subtarget info, allow the asmwriter to do some target sensing 2005-11-21 22:43:58 +00:00
X86Subtarget.h Simplify the subtarget info, allow the asmwriter to do some target sensing 2005-11-21 22:43:58 +00:00
X86TargetMachine.cpp initial step at adding a dag-to-dag isel for X86 backend. Patch contributed 2005-11-16 01:54:32 +00:00
X86TargetMachine.h Add a new option to indicate we want the code generator to emit code quickly,not spending tons of time microoptimizing it. This is useful for an -O0style of build. 2005-11-08 02:11:51 +00:00

//===---------------------------------------------------------------------===//
// Random ideas for the X86 backend.
//===---------------------------------------------------------------------===//

Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
Hi and Lo parts (combination of MUL and MULH[SU] into one node).  Add this to
X86, & make the dag combiner produce it when needed.  This will eliminate one
imul from the code generated for:

long long test(long long X, long long Y) { return X*Y; }

by using the EAX result from the mul.  We should add a similar node for
DIVREM.

another case is:

long long test(int X, int Y) { return (long long)X*Y; }

... which should only be one imul instruction.

//===---------------------------------------------------------------------===//

This should be one DIV/IDIV instruction, not a libcall:

unsigned test(unsigned long long X, unsigned Y) {
        return X/Y;
}

This can be done trivially with a custom legalizer.  What about overflow 
though?  http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224

//===---------------------------------------------------------------------===//

Need to add support for rotate instructions.

//===---------------------------------------------------------------------===//

Some targets (e.g. athlons) prefer freep to fstp ST(0):
http://gcc.gnu.org/ml/gcc-patches/2004-04/msg00659.html

//===---------------------------------------------------------------------===//

This should use faddi on chips where it is profitable:
double foo(double P, int *I) { return P+*I; }

//===---------------------------------------------------------------------===//

The FP stackifier needs to be global.  Also, it should handle simple permutates
to reduce number of shuffle instructions, e.g. turning:

fld P	->		fld Q
fld Q			fld P
fxch

or:

fxch	->		fucomi
fucomi			jl X
jg X

//===---------------------------------------------------------------------===//

Improvements to the multiply -> shift/add algorithm:
http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html

//===---------------------------------------------------------------------===//

Improve code like this (occurs fairly frequently, e.g. in LLVM):
long long foo(int x) { return 1LL << x; }

http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html

Another useful one would be  ~0ULL >> X and ~0ULL << X.

//===---------------------------------------------------------------------===//

Should support emission of the bswap instruction, probably by adding a new
DAG node for byte swapping.  Also useful on PPC which has byte-swapping loads.

//===---------------------------------------------------------------------===//

Compile this:
_Bool f(_Bool a) { return a!=1; }

into:
        movzbl  %dil, %eax
        xorl    $1, %eax
        ret